Oluwamuyiwa O. Olubuyide

High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si heterostructures on insulator

Fully depleted MOSFETs were fabricated on strained Si/strained SiGe (46% Ge)/strained Si heterostructures on insulator (HOI) for the first time, demonstrating both high electron and hole mobility enhancements while maintaining excellent subthreshold characteristics. The total thickness of the heterostructure on insulator is less than 25 nm. At an inversion charge density of 1.5/spl times/10/sup 13/ cm/sup -2/, mobility enhancements of 90% and 107% are obtained for electrons and holes respectively. The mobility increases as the cap thickness is reduced to 2 nm. HOI offers superior hole mobility than 40% strained silicon directly on insulator at all vertical fields, when the cap thickness is below 5 nm.

Strain dependence of Si–Ge interdiffusion in epitaxial Si∕Si1−yGey∕Si heterostructures on relaxed Si1−xGex substrates

The strain dependence of Si–Ge interdiffusion in epitaxial Si∕Si1−yGey∕Si heterostructures on relaxed Si1−xGex substrates has been studied using secondary ion mass spectrometry, Raman spectroscopy, and simulations. At 800 and 880 °C, significantly enhanced Si–Ge interdiffusion is observed in Si∕Si1−yGey∕Si heterostructures (y=0.56, 0.45, and 0.3) with Si1−yGey layers under compressive strain of −1%, compared to those under no strain. In contrast, tensile strain of 1% in Si0.70Ge0.30 layer has no observable effect on interdiffusion in Si∕Si0.70Ge0.30∕Si heterostructures. These results are relevant to the device and process design of high mobility dual channel and heterostructure-on-insulator metal oxide semiconductor field effect transistors.

Effect of thermal processing on mobility in strained Si/strained Si1−yGey on relaxed Si1−xGex (x<y) virtual substrates

Annealing effects on hole and electron mobility in dual-channel structures consisting of strained Si and Si1−yGey on relaxed Si1−xGex layers (x=0.3/y=0.6, and x=0.5/y=0.8) were studied. Hole mobility decreases sharply, but electron mobility is quite immune to annealing conditions of 800 °C, 30 min or 900 °C, 15 s. The hole mobility decrease is more severe in dual-channel structures with higher Ge contents. Hole mobility degradation is a direct result of Ge outdiffusion from the Si1−yGey layer, and the resulting decreased Ge content. Ge diffusion preferentially towards the Si1−xGex buffer layer, rather than the Si cap layer, is a reason that electron mobility is highly immune to such annealing.

Electronic Photonic Integrated Circuits for High Speed, High Resolution, Analog to Digital Conversion

Progress in developing high speed ADCs occurs rather slowly - at a resolution increase of 1.8 bits per decade. This slow progress is mostly caused by the inherent jitter in electronic sampling - currently on the order of 250 femtoseconds in the most advanced CMOS circuitry. Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse trains that show jitter on the level of a few femtoseconds over the time spans of typical sampling windows and can be made even smaller. The MIT-GHOST (GigaHertz High Resolution Optical Sampling Technology) Project funded under DARPAs Electronic Photonic Integrated Circuit (EPIC) Program is trying to harness the low noise properties of femtosecond laser sources to overcome the electronic bottleneck inherently present in pure electronic sampling systems. Within this program researchers from MIT Lincoln Laboratory and MIT Campus develop integrated optical components and optically enhanced electronic sampling circuits that enable the fabrication of an electronic-photonic A/D converter chip that surpasses currently available technology in speed and resolution and opens up a technology development roadmap for ADCs. This talk will give an overview on the planned activities within this program and the current status on some key devices such as wavelength-tunable filter banks, high-speed modulators, Ge photodetectors, miniature femtosecond-pulse lasers and advanced sampling techniques that are compatible with standard CMOS processing.

Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p-MOSFETs

The mobility and subthreshold characteristics of TiN-gate, dual-channel heterostructure MOSFETs consisting of strained-Si-Si/sub 0.4/Ge/sub 0.6/ on relaxed Si/sub 0.7/Ge/sub 0.3/ are studied for strained-Si cap layer thicknesses ranging from 3 to 10 nm. The thinnest Si cap sample (3 nm) yields the lowest subthreshold swing (80 mV/dec) and the highest hole mobility enhancement (2.3X at a vertical effective field of 1 MV/cm). N-MOSFETs show the expected electron mobility enhancement (1.8X) for 10- and 5-nm-thick Si cap samples, which reduces to 1.6X for an Si cap thickness of 3 nm. For Si cap and gate oxide thicknesses both equal to 1 nm, simulations predict a moderate degradation in p-MOSFET subthreshold swing, from 73 to 85 mV/dec, compared to that for the Si control.

Germanium-concentration dependence of arsenic diffusion in silicon germanium alloys

The germanium-concentration dependence of arsenic diffusion in relaxed silicon germanium (Si1−xGex) alloys with Ge content ranging from 0 to 40% has been investigated. Arsenic was implanted into relaxed epitaxial layers at 15 keV to a dose of 3×1015 cm−2, and diffusion during furnace and rapid thermal annealing was studied. Under equilibrium extrinsic conditions, the arsenic diffusivity increases exponentially with increasing Ge content in Si1−xGex. Under transient diffusion conditions, the arsenic diffusivity in Si1−xGex is retarded compared to the diffusivity for longer times, while a slight transient enhancement of As diffusion is observed in Si. The degree of transient retardation depends on the germanium concentration in the alloy.

Mobility and sub-threshold characteristics in high-mobility dual-channel strained Si/strainef SiGe p-MOSFETs

In this work, for the first time, a comprehensive study of mobility, sub-threshold slope and off-state leakage current in high Ge content dual-channel strained Si/strained Si_1-yGe on relaxed Si_1-xGe_x p-MOSFETs is presented. Hole mobility enhancements of 3X are observed at high inversion charge densities (N _inv=10¹³ cm^-2) for the strained Si_0.3Ge_0.7 on relaxed Si_0.7Ge_0.3 (70/30) structure with 2 nm-thick cap, and 3 nm-thick gate oxide. A wide range of Ge fractions and Si cap thicknesses are studied. The mobility enhancement is dominated by the Ge fraction in the strained Si _1-yGe_y layer, while the level of strain is a second order effect. The off-state drain leakage is studied in detail. At low drain-to-gate bias (V_DG), off-state leakage is attributed to a trap assisted tunneling (TAT) mechanism at the Si surface, and is sensitive to Si cap layer thickness. At high V_DGthe leakage increases with the Ge fraction in the strained Si_1-yGe_y and strain in the Si cap layer, consistent with band-to-band tunneling (BTBT). The data illustrates trade-offs critical to optimizing the structures with respect to mobility, charge control, and leakage

Silicon Electronic Photonic Integrated Circuits for High Speed Analog to Digital Conversion

Integrated optical components on the silicon platform and optically enhanced electronic sampling circuits are demonstrated that enable the fabrication of a variety of electronic-photonic A/D converter chips surpassing currently available technology in sampling speed and resolution

Integrated Optical Components in Silicon for High Speed Analog-to- Digital Conversion

Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse trains that show jitter on the level of a few femtoseconds over tens of milliseconds and over seconds if referenced to atomic frequency standards. These low jitter sources can be used to perform opto-electronic analog to digital conversion that overcomes the bottleneck set by electronic jitter when using purely electronic sampling circuits and techniques. Electronic Photonic Integrated Circuits (EPICs) may enable in the near future to integrate such an opto-electronic analog-to-digital converters (ADCs) completely. This presentation will give an overview of integrated optical devices such as low jitter lasers, electro-optical modulators, Si-based filter banks, and high-speed Si-photodetectors that are compatible with standard CMOS processing and which are necessary for the implementation of EPIC-chips for advanced opto-electronic ADCs.

Influence of Strained Si1-yGey Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

Hole mobility enhancement factors from 3x to 10x relative to unstrained Si MOSFETs have been measured in dual channel p-MOSFETs with strained Si1-yGey compositions ranging from y=0.7 to 1 (i.e. up to pure strained Ge) [1,2]. The thickness of both the strained Si cap and the strained SiGe buried channel have a significant impact on mobility in these structures, and understanding these effects is critical to optimizing the device layer structure. In this study we investigate the influence of strained Si0.3Ge0.7 film thickness on hole mobility for strained Si0.3Ge0.7–channel p-MOSFETS. The impact of channel Ge composition between 70% and pure Ge is also investigated and compared to previously published data. Epitaxial layers were grown in an Applied Materials “Epi-Centura” system. The layer structures studied are illustrated in Fig. 1, (a) structure A and (b) structure B. The gate oxide consists of 3nm thermal oxide grown at 600oC or 7nm deposited oxide at 400oC, which were used for structures A and B respectively. The strained SiGe and Ge layers were grown at 450oC and the Si cap layer was grown at 600oC. The Ge composition in the relaxed SiGe layer was fixed at 40% for all structures. The mobility is measured on 50μm x 50μm LxW p-MOSFETs. A tri-layer heterostructure, structure A, with a strained Si layer above and below the strained SiGe channel, is used to investigate the impact of SiGe film thickness on hole mobility. This structure maximizes hole confinement in the strained SiGe channel. In structure B there is weaker hole confinement than in structure A, since the band offset at the strained Si0.3Ge0.7/relaxed Si0.6Ge0.4 interface is 315 meV compared to 470 meV at the strained Si0.3Ge0.7/strained Si interface [3]. The measured hole mobility for strained Si0.3Ge0.7 decreases with decreasing buried SiGe layer thickness (Fig. 2). The mobility enhancement factor relative to Si control devices is shown in Fig. 3. There is a significant decrease in mobility when the SiGe channel thickness is reduced to 4 nm. The simulated hole density profiles (Fig. 4) indicate a decrease of the effective width of the hole density distribution, for a SiGe layer thickness of 4 nm, which may be the origin of the reduced mobility, consistent with observations on heterostructure-on-insulator MOSFETs [4]. Mobility for heterostructure MOSFETs with Ge compositions of 0.8 up to 1 is shown in Fig. 5 (structure B). Hole mobility enhancement of 8x is achieved for a nominally 6nm-thick strained Ge channel, which compares well to previously published results [2, 5]. The hole mobility enhancement measured in this work, at inversion charge densities, Ninv=5 and 10 x 10 cm is shown in Fig. 6, along with previously published values [1,2,5,6]. The mobility results presented in this work provide data across a range of film thickness and Ge concentrations, which is required to model and optimize the performance of high mobility, high-Ge-concentration strained heterostructure p-MOSFETs.