Judy L. Hoyt

Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics

We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous approaches. Our technology supports dense wavelength-division multiplexing with dozens of wavelengths per waveguide. Simulation and experimental results reveal an order of magnitude better energy-efficiency than electrical links in the same technology generation. Exploiting key features of our photonics technology, we have developed a processor-memory network architecture for future manycore systems based on an opto-electrical global crossbar. We illustrate the advantages of the proposed network architecture using analytical models and simulations with synthetic traffic patterns. For a power-constrained system with 256 cores connected to 16 DRAM modules using an opto-electrical crossbar, aggregate network throughput can be improved by ap8-10times compared to an optimized purely electrical network.

Strained silicon MOSFET technology

Mobility and current drive improvements associated with biaxial tensile stress in Si n- and p-MOSFETs are briefly reviewed. Electron mobility enhancements at high channel doping (up to 6 /spl times/ 10/sup 18/ cm/sup -3/) are characterized in strained Si n-MOSFETs. For low inversion layer carrier concentrations, channel-dopant ionized impurity scattering does reduce the strain-induced mobility enhancement, but the enhancement is recovered at higher inversion charge concentrations, where screening is efficient. Mobility enhancement in strained Si p-MOSFETs is also discussed. There are process integration challenges and opportunities associated with this technology. Dopant diffusion, and its impact on profile engineering in strained Si CMOS structures, is one example. While the slower diffusion of B in Si/sub 1-x/Ge/sub x/ enables improved doping profile control, the diffusivity of the n-type dopants is dramatically enhanced in Si/sub 0.8/Ge/sub 0.2/.

Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si/sub 0.75/Ge/sub 0.26/ and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si/sub 1-x/Ge/sub x/ layer.

Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate- controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si0.5Ge0.5 hetero- junctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (Vdd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.

Photonic ADC: overcoming the bottleneck of electronic jitter

Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated for many years as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits using a photonic ADC built from discrete components. This accuracy corresponds to a timing jitter of 15 fs - a 4-5 times improvement over the performance of the best electronic ADCs which exist today. On the way towards an integrated photonic ADC, a silicon photonic chip with core photonic components was fabricated and used to digitize a 10 GHz signal with 3.5 effective bits. In these experiments, two wavelength channels were implemented, providing the overall sampling rate of 2.1 GSa/s. To show that photonic ADCs with larger channel counts are possible, a dual 20-channel silicon filter bank has been demonstrated.

Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics

Silicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks.

Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations

A simple model that links MOSFET performance, in the form of intrinsic switch delay, to effective carrier velocity in the channel is developed and fitted to historical data. It is shown that nearly continuous carrier velocity increase, most recently via the introduction of process-induced strain, has been responsible for the device performance increase commensurately with dimensional scaling. The paper further examines channel material innovations that will be required in order to maintain continued commensurate scaling beyond what can be achieved with process-induced strain, and discusses some of the technological tradeoffs that will have to be faced for their introduction.

Localized substrate removal technique enabling strong-confinement microphotonics in bulk Si CMOS processes

A novel post-processing fabrication technique, based on XeF2 etching, has been developed to locally remove the silicon substrate beneath polysilicon waveguides, enabling integration of low-loss strong-confinement microphotonics into standard bulk-silicon CMOS process flows.

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.

Strained-

Strained pseudomorphic Si/Si1-xGex/Si gate-controlled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration in the 1019-1020 cm-3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are compared to simulations using a nonlocal BTBT model to analyze the mechanisms of device operation and to understand the impact of these parameters on the device switching behavior. The measured characteristics are consistent with simulation analysis that shows a reduction in energy barrier for tunneling (Egeff) and a reduction in tunneling distance with increasing Ge composition and source doping concentration. Increases in the pseudomorphic layer Ge content and doping concentration of the tunnel junction produce large improvements in the measured switching-behavior characteristics (Ion, slope, turn-on voltages, and sharpness of turn-on as a function of Vds). Simulations are also performed to project the potential performance of more optimized structures that may be suitable for extremely low power applications (Vdd < 0.4 V).