Omar Elkeelany

Performance analysis of IPSec protocol: encryption and authentication

IPSec provides two types of security algorithms, symmetric encryption algorithms (e.g. data encryption standard DES) for encryption, and one-way hash functions (e.g., message digest MD5 and secured hash algorithm SHA1) for authentication. This paper presents performance analysis and comparisons between these algorithms in terms of time complexity and space complexity. Parameters considered are processing power and input size. The analysis results revealed that HMAC-MD5 can be sufficient for the authentication purposes rather than using the more complicated HMAC-SHA1 algorithm. In encryption applications, authentication should be combined with DES.

A Low-Cost Stand-Alone Multichannel Data Acquisition, Monitoring, and Archival System With On-Chip Signal Preprocessing

The objective of this paper is to design a new generation of affordable sophisticated data acquisition and processing (DAQP) systems. Because of the proposed system hardware reconfigurability, it can be used to meet the need of many real-world applications while keeping the cost of a device low. The hardware implementation of the different processing functions of the device allows for high-speed processing without the need of expensive general-purpose processors, as is the case of computer-based or microcontroller-based data acquisitions (DAQs). The target technology of implementing the proposed design is the system on chip via field-programmable gate array (SoC-FPGA). A four-channel DAQP was designed, developed, and tested in the Embedded Systems Design Laboratory, Tennessee Technological University, Cookeville. Various modules of the conceptual design are implemented and verified. Performance evaluation and cost comparisons are provided. The comparison showed that the results of the proposed instrument are comparable to existing technologies at a fraction of the cost.

Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware

With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent confidentially over the network without fear of hackers or unauthorized access to it. This makes security implementation in networks a crucial demand. Symmetric Encryption Cores provide data protection via the use of secret key only known to the encryption and decryption ends of the communication path. In this paper, first, an overview of two well known symmetric encryption cores is presented, namely the 3DES and RC5. Then a performance evaluation of their computer based implementation is compared to demonstrate the RC5 superior performance. The conventional hardware architecture of the RC5 core is presented and investigated. A hardware system design is proposed to improve its performance. The proposed architecture achieved with three stage pipeline technique an increased encryption throughput as compared to related work. By exploiting modern features in Field Programmable Gate Arrays (FPGA), which allow the modeling of a System-on- Programmable-Chip (SoPC), this paper proposes a model for symmetric encryption algorithms ( e.g., RC5). Structural System analysis of the proposed model shows that it offers extra security against single-site physical access attack that other implementations are vulnerable to. By evaluating the performance of this proposed SoPC model, one finds that it raises the encryption throughput to 300 Mbps. Hence, we report over 80% increase in the encryption throughput as compared to related work. Moreover, our work lowers the implementation cost due to the integration of all system parts into one chip.

A Survey on Data Acquisition Systems DAQ

Data acquisition systems have been used in various applications in our world. Numerous techniques and algorithms have been employed to achieve high quality acquisition. Each application has its own philosophy and data acquisition structure. Hence, in this paper, a survey on data acquisition systems has been presented. Different DAQ categories have been introduced. A comparison study between these categories has been presented. Different applications that need DAQs have been mentioned in more details illustrating DAQ technique used for each application.

System-On-Chip technology-based on-the-fly audio data acquisition, monitoring and displaying system using FPGA

Data monitoring can be defined as signals and waveforms capturing and processing to obtain desired information. Prior to data monitoring, a data acquisition component may be applied. The data acquisition component utilizes sensors that convert any measurement parameter to an electrical signal, which can be monitored and displayed into a display module. Displaying data on the field on-the-fly is needed in many applications. In this research, a novel reconfigurable system design and implementation are proposed using system-on-chip technology. This proposed system is responsible for real-time varying audio data acquisition, analog to digital conversion, processing the digital data, and displaying the data into a display module.

Performance evaluation of hardware models of Advanced Encryption Standard (AES) algorithm

In todays world most of the communication is done using electronic media. Data Security plays a vital role in such communication. Hence, there is a need to protect data from malicious attacks. Advanced Encryption Standard (AES), also known as Rijndael, is an encryption standard used for securing information. AES is a block cipher algorithm that has been analyzed extensively and is now used widely. The hardware implementation of AES algorithm is faster and more secure than software implementation. There are different hardware models to implement the Rijndael Encryption core. This paper addresses the performance of Rijndael AES Encryption algorithm of key length 128 bits. Two hardware models based on HDL and IP core are used to evaluate the performance of the algorithm. The encryption time and also the performance metrics such as size, speed and memory utilization are evaluated, using these models. Results are compared to a reference model and have shown an increase in the throughput per slice measure.

SPEED: Stand-alone programmable ethernet enabled devices ☆

Abstract In this paper we present the design and synthesis of Standalone Programmable Ethernet Enabled Devices (SPEED) as a low cost and power consumption embedded system, which also include an Electrical Erasable Programmable Read Only Memory controller for configurable address assignments. The main function of SPEED is to eliminate the operating system processing of network protocol stack running by personal computer processor and simplifying network functions. This simplification is not exclusively required to fit in a hardware solution, but more important it improves network performance. It utilizes the concept of network channels, where Ethernet frames are delivered through a custom multicast addressing scheme. After validating SPEED simulation outputs, we synthesize the design in FPGA chip using Verilog HDL. Performance measures like power consumption and area utilization are computed using Verilog HDL synthesis tools. Initial performance measures had shown that the SPEED would be reducing the power consumption. Consequently, network devices could be powered through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. This way, SPEED reduces the installation complexity, especially for large number of devices (e.g. surveillance cameras).

Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs

Hardware security is a major concern in the intellectual property (IP) centric integrated circuits (IC). 3-D IC design augments IP centric designs. However, 3-D ICs suffer from high temperatures in their middle tiers due to long heat dissipation paths. We anticipate that this problem would exacerbate the hardware security issues in 3-D ICs. Because, high temperature leads to undesired timing characteristics in ICs. In this paper we provide a detailed analysis on how these delay variations can lead to non-ideal behavior of control paths. It is demonstrated that a hardware intruder can leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. Our simulation results show that a state machine can lead to temporary glitches long enough to cause malfunctioning at temperatures of 87°C or above, under nominal frequencies. The overall area overhead of the payload compared to a very small Mod-3 counter is 6%.

Data Archival to SD Card Via Hardware Description Language

The main objective of this letter is to present the design of an efficient, real-time data archival system to a secure digital flash memory card via reconfigurable hardware. The data access from the SD card is implemented completely using Verilog and hence, there is no use of any microcontroller or on-chip general purpose processors. And since the complete design is a single-purpose system, no extra hardware is required. The design has four independent modules for the required different operations on the SD memory card. These four modules are for single-block write, multiple-block write, single-block read, and multiple-block read operations. We show how the bidirectional access takes place correctly and the data integrity has been verified using cyclic redundancy code in both field-programmable gate array (FPGA) chip and the SD card controller.

Reconfigurable wireless stand-alone platform for Electrical Capacitance Tomography

This paper presents the assessment of using Field Programmable Gate Arrays (FPGA) technology to design a stand-alone Electrical Capacitance Tomography (ECT) system. ECT application is manifested by computationally intensive image reconstruction algorithms requiring fast processing of large amounts of data. To date, reconfigurable hardware has not been used in the area of electrical tomography. Furthermore, the experimental results show that using the FPGA as a hardware platform to realize ECT system achieves superior performance in terms of speed and design compactness compared to DSP implementation.