Orly Yadid-Pecht

Wide intrascene dynamic range CMOS APS using dual sampling

A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64/spl times/64 element prototype sensor with dual output architecture was fabricated using a 1.2 /spl mu/m n-well CMOS process with 20.4 /spl mu/m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding.

A random access photodiode array for intelligent image capture

A chip implementing random scan was designed, fabricated, and tested. The chip covers the basic requirements for random access and separation between the sampling and reading processes. In this way, a repeated reading of any pixel at any time can take place. The chip includes an 80*80 matrix of basic cells. Each cell consists of two stages: The first is based on a switch, whereas the second includes a buffer. The chip was fabricated in a 3- mu m CMOS process. It was found to operate functionally. However, the use of a standard process gave rise to the crosstalk phenomenon, which has yet to be overcome. >

CMOS active pixel sensor star tracker with regional electronic shutter

A 64/spl times/64 element CMOS active pixel sensor (APS) for star tracker applications is reported. The chip features an innovative regional electronic shutter through the use of an individual pixel reset architecture. Using the regional electronic shutter, each star in the field of view can have its own integration period. This way, simultaneous capture of bright stars with dim stars is accommodated, enabling a large increase in tracker capability. The chip achieves 80 dB dynamic range, 50 e-rms read noise, low dark current, and excellent electronic shutter linearity.

Wide-Dynamic-Range CMOS Image Sensors—Comparative Performance Analysis

A large variety of solutions for widening the dynamic range (DR) of CMOS image sensors has been proposed throughout the years. We propose a set of criteria upon which an effective comparative analysis of the performance of wide-DR (WDR) sensors can be done. Sensors for WDR are divided into seven categories: 1) companding sensors; 2) multimode sensors; 3) clipping sensors; 4) frequency-based sensors; 5) time-to-saturation (time-to-first spike) sensors; 6) global-control-over-the-integration-time sensors; and 7) autonomous-control-over-the-integration-time sensors. The comparative analysis for each category is based upon the quantitative assessments of the following parameters: signal-to-noise ratio, DR extension, noise floor, minimal transistor count, and sensitivity. These parameters are assessed using consistent assumptions and definitions, which are common to all WDR sensor categories. The advantages and disadvantages of each category in the sense of power consumption and data rate are discussed qualitatively. The influence of technology advancements on the proposed set of criteria is discussed as well.

Effective Lifetime-Aware Routing in Wireless Sensor Networks

Lifetime-aware routing and desired sensing spatial coverage (SSC) are two main challenges ahead of an ad-hoc, sensor-based, battery operated monitoring system known as wireless sensor network (WSN). Depending on the application, a necessary SSC level is essential to comply with the needed surveillance quality. On the other hand, network lifetime is of a major concern due to limited energy available to each sensor node. Formerly proposed lifetime-aware routing algorithms have usually defined lifetime as the duration before the first node runs out of energy. This criterion is not consistent with real-world WSN, where a number of sensors are likely to “die” due to hardware failures, natural impacts, etc. Initially, we propose a method that determines the network resource specifications, i.e., the number of available nodes and their sensing range, according to the required SSC and the necessary confidence level. Later on, a novel lifetime criterion which considers the SSC as the WSN effective operation criterion is introduced. Afterward, the new criterion is embedded into the flow augmentation algorithm and the normalized network lifetime is calculated for several scenarios using the solutions of the corresponding linear programming equations. Simulation results show significant improvement achieved in the lifetime. It is also shown that this new method is considerably more robust to the routing algorithm parameters compared to the performance achieved by the published Flow Augmentation algorithm.

Quaternion Structural Similarity: A New Quality Index for Color Images

One of the most important issues for researchers developing image processing algorithms is image quality. Methodical quality evaluation, by showing images to several human observers, is slow, expensive, and highly subjective. On the other hand, a visual quality matrix (VQM) is a fast, cheap, and objective tool for evaluating image quality. Although most VQMs are good in predicting the quality of an image degraded by a single degradation, they poorly perform for a combination of two degradations. An example for such degradation is the color crosstalk (CTK) effect, which introduces blur with desaturation. CTK is expected to become a bigger issue in image quality as the industry moves toward smaller sensors. In this paper, we will develop a VQM that will be able to better evaluate the quality of an image degraded by a combined blur/desaturation degradation and perform as well as other VQMs on single degradations such as blur, compression, and noise. We show why standard scalar techniques are insufficient to measure a combined blur/desaturation degradation and explain why a vectorial approach is better suited. We introduce quaternion image processing (QIP), which is a true vectorial approach and has many uses in the fields of physics and engineering. Our new VQM is a vectorial expansion of structure similarity using QIP, which gave it its name-Quaternion Structural SIMilarity (QSSIM). We built a new database of a combined blur/desaturation degradation and conducted a quality survey with human subjects. An extensive comparison between QSSIM and other VQMs on several image quality databases-including our new database-shows the superiority of this new approach in predicting visual quality of color images.

Hybrid Integration of an Active Pixel Sensor and Microfluidics for Cytometry on a Chip

Reported are motivations and approaches for the integration of custom sensors with microfluidic devices for cytometry on a chip and related fluid metering applications. To demonstrate, details of a digital 16-element mixed-signal CMOS active pixel optical sensor with adaptive spatial filtering is first described. The 0.18-mum CMOS fabricated sensor is then shown coupled to a microfluidic channel via a polymer encapsulated chip-on-board approach as well as a preferred flip-chip-on-glass hybrid integration approach. However, both approaches discussed possess attributes that are well suited for reliable high-volume production. Utilizing these two disparate assembly topologies, the intelligent sensors general behavior, optical input dynamic range, and near-field sensitivity to polymer beads being transported in a microfluidic channel is explored. The findings suggest that discrete near-field sensor integration with microfluidics is a well-positioned integration approach for helping to obviate the need for precision analog-to-digital conversion, optical fiber microchannel coupling, and conventional microscopy for a set of relevant micro total analysis system applications. By opting instead for a hybrid multichip module approach to system integration, this study marks a slight departure in strategy relative to many common monolithic system-on-chip integration efforts

CMOS Image Sensors With Self-Powered Generation Capability

Considerations for CMOS image sensors with self-power generation capability design are presented. Design of CMOS imagers, utilizing self-powered sensors (SPS) is a new approach for ultra low-power CMOS active pixel sensors (APS) implementations. The SPS architecture allows generation of electric power by employing a light sensitive device, located on the same silicon die with an APS and thus reduces power dissipation from the conventional power supply. A detailed analysis of the SPS structure is carried out, with respect to power dissipation requirements, sensor area and power generation efficiency, showing advantages and drawbacks of the proposed concept. An illustrative example of CMOS imager with self-power generation capability in 0.18-mum standard CMOS technology is discussed. Measurements from a test chip, implemented in 0.18-mum CMOS process, are presented

CMOS image sensor with watermarking capabilities

The problem of authenticity for digital images has been helped by the development of digital watermarking. As an extension of the current state-of-the-art, a CMOS active pixel sensor (APS) imager with built-in watermarking of the output image is presented. A method for generation of watermarks specific to each chip is presented as well as simulations showing the effectiveness of the watermarking algorithm. The layout was designed in TSMCs 0.18 /spl mu/m 1.8/3.3 V process and circuit simulations indicate performance as expected.

Hardware Implementation of a Digital Watermarking System for Video Authentication

This paper presents a hardware implementation of a digital watermarking system that can insert invisible, semifragile watermark information into compressed video streams in real time. The watermark embedding is processed in the discrete cosine transform domain. To achieve high performance, the proposed system architecture employs pipeline structure and uses parallelism. Hardware implementation using field programmable gate array has been done, and an experiment was carried out using a custom versatile breadboard for overall performance evaluation. Experimental results show that a hardware-based video authentication system using this watermarking technique features minimum video quality degradation and can withstand certain potential attacks, i.e., cover-up attacks, cropping, and segment removal on video sequences. Furthermore, the proposed hardware-based watermarking system features low power consumption, low cost implementation, high processing speed, and reliability.