Osama Shana'a

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS

In recent years, the increasing popularity of mobile devices, such as smart- phones and tablets, is driving the demand for integrating multiple radios on a single SoC to reduce cost, form factor and external BOM. These devices require ubiquitous wireless connectivity, which means concurrent operation with different radios. While concurrent operation of multiple radios brings excellent user experiences, there exist great challenges in dealing with radio co-existence in an SoC. For example, concurrent operation between WiFi and BT, both oper- ating in the 2.4GHz ISM band, sets additional requirements in RF front-end cir- cuits and system control. In addition, thermal effect of the integrated WiFi PA needs to be compensated to minimize its impact on the frequency-precise GPS system.

A harmonic-rejection mixer with improved design algorithm for broadband TV tuners

A wide-band harmonic rejection mixer for TV tuners with an improved design algorithm is fabricated in 65-nm CMOS process. A more realistic mathematical formula is derived to calculate harmonic rejection performance. The third and fifth order harmonic rejection ratio calculation, based on the new proposed equations, precisely predicts simulation results. A systematic design optimization technique pushes the mean of the harmonic rejection performance to a higher value resulting in better yield. The measured third and fifth order harmonic rejection ratio for 2000 samples is better than -56dBc for VHFI and II bands without increasing any circuit complexity or implementation difficulty.

A universal GNSS (GPS/Galileo/Glonass/Beidou) SoC with a 0.25mm 2 radio in 40nm CMOS

Global Navigation Satellite Systems (GNSS) have a spectrum allocation shown in Fig. 19.4.1. The time-to-first-lock and location accuracy can be improved through simultaneous reception of two different satellite signals. This usually necessitates the use of two dedicated receivers [1] driven by a single and sometimes two separate synthesizers, which increases complexity, die area, and most importantly current consumption. To solve this problem, the architecture shown in Fig. 19.4.1 is proposed. The SoC consists of one single reconfigurable low-IF receiver, a single fractional-N frequency synthesizer, and a digital baseband processor. Since different satellite signals are uncorrelated and are buried well below the noise floor, they can be amplified and downconverted by the same RF/analog chain as an image of one another, and then separated in the digital domain by the corresponding correlator and signal processor. In the case of simultaneous GPS/Galileo and Glonass dual reception, the LO (fLO_GG) is set to 1588.608MHz. As a result, the GPS/Galileo signal becomes the image of the Glonass satellite signal with an IF frequency of 13.1MHz. Similarly, when the LO (fLO_GB) is set to 1568.256MHz, the resulting IF frequency is about 7.1MHz for GPS/Galileo and Beidou dual reception. For GPS/Galileo-only reception, the LO (fLO_GPS) is set to 1571.328MHz resulting in an IF frequency of 4.092MHz.

An Ultra-Low-Cost High-Performance Bluetooth SoC in 0.11-

A highly integrated ultra-low-cost high-performance Bluetooth 3.0+EDR SoC is implemented in 0.11-μm digital CMOS technology. The transceiver has an integrated balun shared between TX and RX, eliminating the need for a separate T/R switch. A 4 × LO-based VCO is implemented to reduce LO pulling and to minimize TX out-of-band spurious emissions. The transmitter provides high output power of +10 and +7 dBm in BDR and EDR3 modes respectively, with 1.5-kHz frequency stability and <; 6% rms DEVM. The receiver sensitivity is -95.5, - 96.5, and -89 dBm for BDR, EDR2, and EDR3 modes respectively. Total SoC DC current consumption for continuous TX transmission at +10 dBm output power is 48 mA and for continuous RX reception at reference sensitivity level is 35 mA. Total die size is 5.7 mm2, of which 1.8 mm2 is occupied by RF, analog, and PMU circuits.

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The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet the requirements of low noise and multi-radio coexistence. Nevertheless, it is highly desirable to remove the external LNA and interstage SAW filter due to size and cost, which presents a great design challenge to achieve high out-of-band linearity with very low power consumption. To fulfill these stringent requirements, a more comprehensive approach is needed to target a radio architecture with a proper RX system budgeting and optimal circuit design. In addition, a GPS system can be desensitized by unexpected in-band blockers generated from other subsystems on the same platform, such as LCD display, PMU, CPU system clocks, etc. The GPS digital baseband processor must possess the capability to withstand in-band blockers without significant performance degradation. This paper presents a GPS/Galileo SoC with an adaptive in-band blocker cancellation scheme, which is implemented in a 65nm CMOS process.

CMOS

Digital transmitters (DTX) have gained interest in the past few years because of their potential to provide compact die area, better efficiency due to the switching nature of the power amplifier core, and scaling with CMOS technology [1-3]. Quadrature DTX architecture [1] is favored over polar [3] or outphasing [4] for wideband applications, such as WiFi, because of its ability to scale easily to higher signal bandwidth. Moreover, there is no need for a CORDIC block to convert I/Q signals to amplitude/phase signals [3], which results in large-signal bandwidth expansion, nor the need for very precise alignment [3,4] using fast digital circuits and excessive calibrations. However, the promised potential of quadrature DTX technology fell short of what has been expected because of the excessive parasitics at the TX output as a result of the traditional way of combining the two I and Q paths at the PA output [1]. An I/Q power-cell sharing method by time-division multiplexing between local oscillator (LO) I/Q signals has been proposed for a low-band cellular DPA (800MHz) to address this problem [2]. However, the technique requires 25% LO, which is very difficult to realize for the 5.5GHz WiFi band and is very power hungry. The DTX in Fig. 9.5.1 addresses this issue through a different method of I and Q combining as well as a new digital baseband signal mapping for a compact die area, low parasitics at the PA output, lower loading on LO lines and better overall efficiency.

A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS

The popularity of the Near-Field Communication (NFC) system stems from being able to establish communication by merely being in the vicinity of another NFC device, an operation known as “tap and go”. An NFC device is quite complex: it has to support both ASK/BPSK modulation, variable data rates from 106kb/s to 848kb/s, different ASK modulation indices (8% to 100%), different card types (NFC-A/B/F), and various coding. It also has different operating modes such as Proximity-Inductively-Coupled Card (PICC) or card-emulation mode, Proximity-Coupled-Device (PCD) or reader mode and Peer-to-Peer (P2P) mode. Furthermore, some PCDs transmit NFC-A/B/F ASK data in a polling loop manner. Therefore, PICC receivers must support joint data-type detection for successful communication with such PCDs. The device shown in Fig. 9.1.1 supports all these operating modes and complies with ISO-14443, ISO-18092 and NFC Forum standards. The SoC has an ultra-low current receiver, a digital transmitter with a 250mA-maximum-current-drive Class-D PA, a Single-Wire Protocol (SWP) supporting two external UICC SIM cards and one micro-SD chip, an energy-harvesting rectifier unit, an agile synthesizer, and a digital modem. Traditionally, two separate receivers with respective synthesizers and clock recovery/generation circuits are adopted for PICC, PCD and P2P modes [1,2]. In addition, three parallel analog demodulators are needed (one each for NFC-A, B and F) to support joint data-type detection, thus increasing die area significantly. The focus of this paper is the adoption of a single receiver with one reconfigurable PLL to support all NFC modes for compact die area.

9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS

Low-distortion I/Q baseband filters interface with a 2.5 GHz RF receiver front-end configured as a Gm-cell in a direct-conversion architecture targeted towards WLAN 802.11b application. The active I/Q current-mode filters use AC current to carry the large swing of both desired and blocker signals, relaxing the voltage headroom requirement to a 1.2 V supply. An on chip master-slave automatic tuner is used to lock the filter bandwidth to a precision 20 MHz reference crystal oscillator, resulting in a <3% tuning accuracy and <0.5% I/Q bandwidth matching. The receiver achieves a 3.2 dB DSB NF, -14 dBm out-of-band IIP3, and + 27 dBm worst case IIP2, all referred to the LNA input, while drawing 30 mA from a 2.7 V supply. The chip is fabricated in a 0.5 mum 46 GHz fT SiGe BiCMOS process. The active area is 2.54 mm2.

9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS

A highly-integrated, ultra-low-cost Bluetooth SOC implemented in 0.11μm digital CMOS technology is disclosed. To reduce BOM count and cost, an integrated balun is designed for the transceiver front-end. A 4xLO based VCO is implemented to reduce LO pulling, and minimize TX out-of-band spurious in the direct-conversion transmitter. The transmitter provides high output power at +10dBm and +7dBm in BDR and EDR3 modes respectively, with 1.5-kHz frequency stability and <6% RMS DEVM The receiver sensitivity is better than −95.5dBm, −96.5dBm and −89dBm for BDR, EDR2 and EDR3 modes respectively. DC current consumption for continuous TX transmission at +10dBm output power is 48mA, and for continuous RX reception at reference sensitivity level is 35mA. Total die size is 5.7mm2, of which 1.8mm2 is occupied by RF, analog and PMU circuits.

A 2.4–2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters

For compact integration of 13.56MHz NFC functionality in mobile devices, a small planar loop antenna is a necessity. Active load modulation (ALM) is a commonly adopted technique to boost load modulation amplitude to overcome weak inductive coupling in small antennas. However, due to the challenges of phase synchronization, ALM is mainly limited to low data rate NFC applications. This paper describes the challenges of supporting NFC Very High Bit Rate (VHBR) Card Emulation Mode (PICC) in small antennas. An ultra-fast retimed phase synchronization PLL technique is proposed to overcome the technical challenges of ALM for high data rate uplink transmission. A sub-sampling ADC topology is implemented as VHBR ASK envelope demodulator. A clock extractor-based PLL provides precise synchronized continuous clock to the high speed sub-sampling ADC for accurate demodulation of all ASK envelopes with modulation index (MI) ranging from 8% to 100%.