Osamu Ikenaga

Triangular Shaped Beam Technique in EB Exposure System EX-7 for ULSI Pattern Formation

The generation of a triangular and rectangular shaped beam is very useful in increasing throughput for writing ULSI patterns which often include many oblique lines. To make use of these shaped beams in ULSI pattern formation, a new rectangular and triangular shaped beam calibration method has been developed on the EB exposure system EX-7. The shaped beam calibration method is established by analyzing the beam current of shaped beams and the backscattered electron signal from a fine gold particle on the target. Resultant accuracies were 0.013 µm for a beam size of 1.6 µm and 0.025 %micro;m for the relative beam position on the target. Using this method, 0.2 µm ULSI patterns including oblique lines have been accurately formed.

Flexible mask specifications

As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing. This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.

Reduction of resist charging effect by EB reticle writer EBM-7000

The requirement for image placement accuracy on photomask has been rising. The ITRS road map says that we need to achieve 4.3nm accuracy in 2012 for HP 36nm device with single exposure process, further more we must achieve 3.0nm accuracy if double patterning process is selected. Fig.1 shows the todays performance of image placement accuracy. Some sample photomasks which have same pattern shape are produced during 3 months, and the mask to mask overlay accuracy of them was measured. The average of them was 3.6nm. This data shows the possibility to achieve the accuracy of photomask for HP 36nm devices. The image placement accuracy of actual device pattern during same period is showed in Fig.2. The image placement accuracy of actual device pattern is worse than that showed before. We categorized these data according to the pattern density, low density pattern and the high density pattern. The density of the test pattern is categorized into very low density pattern. The results are showed in Fig.3. We can see the degrading of image place accuracy according to the pattern density. This degrading of image placement accuracy is caused by resist charging effect. In photomask production process, electron beam writer is mainly used as lithography tool. Each pattern on photomask is formed by step by step exposure of electron beam. The surface of resist film will be charged with exposed electron beam, and electric field will be generated around that charged area. So the orbit of electron beam for next exposure will be bended by the electric field which generated by previous beam shot, and image placement accuracy will degrade. To achieve the demanded image placement accuracy, we need to remove the error caused by this phenomenon. We researched in resist charging effect for correcting it, and we studied that this phenomenon have so complex feature. After that we tried to research in it on EBM-7000, newly developed electron beam writer, and we found out the reduction of the image placement error caused by the resist charging effect on EBM-7000.

1nm of local CD accuracy for 45nm-node photomask with low sensitivity CAR for e-beam writer

We achieved highly accurate Local CD in the vicinity of 1nm with the newly developed low sensitivity chemically amplified resist (CAR) for the e-beam reticle writer, EBM-6000. We applied shot noise model to estimate Line Edge Roughness (LER). According to the estimation result, LER is improved by increasing the threshold dosage. We evaluated the performance of newly developed low sensitivity CAR. Local CD accuracy, LER, pattern resolution and drawing time are evaluated. We concluded that the performance with the low sensitivity CAR was good enough to produce photomasks for 45nm half pitch (HP) devices.

Optical proximity correction feature extraction method using reticle scanning electron microscope images

Optical proximity correction (OPC) features are frequently used in photolithography. It is necessary to measure the shape characteristics such as height, width, area, position of center of gravity, and corner-rounding with nm-order accuracy. For this purpose, critical-dimension scanning electron microscope (CD-SEM) images are utilized. However, it is difficult to extract the shape characteristics mentioned above from a corrected pattern with conventional CD-SEM measurement. The authors developed a method to extract the shape characteristics automatically from a corrected reticle pattern with high accuracy, with combination of discriminant analysis and nonlinear regression.

Shape Data Operations for VSB LB Data Conversion Using CAD Tools

For fast electron beam (EB) data conversion, an improved system of hierarchical process has been constructed. Several functions have been added to hierarchically perform shape data operations with increased efficiency. The added functions aim to cut redundant checks in oversizing, to reduce shape data expansion in array data handling and to speed cell overlap checks. These functions were implemented on a computer-aided design (CAD) system utilizing software tools available on it. The new system was applied to the variable shaped beam (VSB) EB data conversion and demonstrated to have better performance. A 16 Kbit SRAM design, conventionally degenerated near a flat level process, was successfully processed in a hierarchical manner, and performance gains of 1.6 to 3.1 were obtained.

Mask image position correction for double patterning lithography

Application of double patterning technique has been discussed for lithography of HP 3X nm device generation. In this case, overlay budget for lithography becomes so hard that it is difficult to achieve it with only improvement of photomasks position accuracy. One of the factors of overlay error will be induced by distortion of photomask after chucking on the mask stage of exposure tool, because photomasks are bended by the force of vacuum chucking. Recently, mask flatness prediction technique was developed. This technique is simulating the surface shape of mask when it is on the mask stage by using the flatness data of free-standing state blank and the information of mask chucking stage. To use this predicted flatness data, it is possible to predict a pattern position error after exposed and it is possible to correct it on the photomask. A blank supplier developed the flatness data transfer system to mask vender. Every blanks are distinguished individually by 2D barcode mark on blank which including serial number. The flatness data of each blank is linked with this serial number, and mask vender can use this serial number as a key code to mask flatness data. We developed mask image position correction system by using 2D barcode mark linked to predicted flatness data, and position accuracy assurance system for these masks. And with these systems, we made some masks actually.

A photomask defect evaluation system

Photomasks are currently inspected based on the standard of defect size. A shortcoming of this standard is that the type of defects which do not impact on a wafer, could be detected as impermissible defects. All of them are subject to repair works and some of them require further inspection by AIMS. This is one of the factors that are pushing down the yield and the turnaround time (TAT) of mask manufacturing. An effective way to improve this situation will be to do the repair works selectively on the defects that are predicted to inflict a functional damage on a wafer. In this report, we will propose a defect evaluation system named ADRES (Advanced Photomask Defect Repair Evaluation System), featuring a function to extract edges from a mask SEM image to be passed on to a litho-simulation. A distinctive point of our system is the use of a mask SEM image with a high resolution.

Mask Quality Assurance in Cleaning for Haze Elimination Using Flexible Mask Specifications

We propose a new method of quality assurance for attenuated phase shifting mask (PSM) using the concept of the flexible mask specifications to extend the life of PSM [1]. The haze on PSM is a major issue for ArF lithography in semiconductor device manufacturing since it causes decline of device yield. PSM irradiated by ArF laser is periodically cleaned before haze is printed on wafer, which is a killer defect. Repetition of cleaning causes great changes of properties, i.e. phase, transmittance. Therefore, the number of times cleaning is performed has been limited by predetermined specifications based on ITRS. In this paper, relaxation of the pass/ fail criteria are studied as one solution to this limitation problem. In order to decide a suitable number of times for cleaning to be performed, we introduce the concept of flexible mask specifications, taking lithography margin into account. Firstly, we obtained mask parameters before cleaning; these parameters were, for instance, phase, transmittance and CD. Secondly, using these parameters, we simulated images of resist pattern exposed on wafer and obtained exposure latitude at desired depth of focus. Thirdly, we simulated mask parameters and exposure latitude when the mask was cleaned several times and obtained correlation between number of times cleaning is performed and exposure latitude. And finally, we estimated suitable pass/ fail criteria of mask parameters and the maximum number of times cleaning should be performed for each mask at the standard exposure latitude. In the above procedure, the maximum number of times cleaning should be performed exceeded that determined in the case of conventional specifications based on ITRS.

Mask defect specifications with fail-bit-map analysis

A new mask methodology of mask defect specifications by fail-bit-map (FBM) analysis of LSI devices was proposed. In this paper, concept of new mask defect specifications based on the FBM analysis is shown and impacts on LSI devices of mask defects are studied and the new methodology for next generation is applied. The new mask defect specifications were implemented in a gate-level mask with defects programmed into a 0.175μm-rule DRAM fabrication process, as follows, Firstly, the programmed defects varied in terms of the types, locations and sizes were designed into the memory cell area on the 0.175μm-rule DRAM gate-level mask. Secondly, the gate-level mask with programmed defects was fabricated with conventional mask process flow and the actual mask defect sizes were measured. Thirdly, exposures of the gate-level mask were carried out with conventional 0.175μm-rule DRAM process. Finally, the large impacts on CDs caused by mask defect printability on wafers were clarified and FBM analysis was performed to characterize the relationship among the actual mask defect variations, the CD variations and electrical function of 0.175μm-rule DRAM. This relationship can facilitate determination of the mask defect specifications on 0.175μm-rule DRAM and also likely contribute to estimate next-generation defect specifications. According to the results of the above procedure, the mask defect specifications for opaque defects should be generally tighter than those for clear defects in view of the printability on the wafers and the FBM analysis. Nevertheless, the FBM results suggested that current mask inspection sensitivity for clear defects was too high. With the new methodology, in regard to the impacts of mask defects not only on wafer CDs but also on LSI devices, we have succeeded in obtaining useful results for the mask defect specifications.