Masamitsu Itoh

The origin of stress in sputter‐deposited tungsten films for x‐ray masks

The mechanism for the cause of stress in a sputter‐deposited tungsten (W) film has been clarified. The tensile stress of the film was calculated using the interatomic forces acting on the grain boundary. The average distance of the grain boundary gaps was determined from the measured film density assuming the film had homogeneous size rectangular grains. The calculated and measured stress values were in good agreement in the high working gas pressure region. The difference between these values in the low working gas pressure region has been able to be explained by the compressive stress due to the peening effect of Ar. The low stress in the high pressure region was obtained by large opened grain boundaries which produced low film density. A low film density causes a low x‐ray stopping power. The film deposited in the low pressure region is suitable as an x‐ray absorber because of its high film density.

Performance of EBeyeM for EUV Mask Inspection

According to the ITRS Roadmap, the EUV mask requirement for 2X nm technology node is detection of defect size of 20 nm. The history of optical mask inspection tools involves continuous efforts to realize higher resolution and higher throughput. In terms of productivity, considering resolution, throughput and cost, we studied the capability of EUV light inspection and Electron Beam (EB) inspection, using Scanning Electron Microscope (SEM), including prolongation of the conventional optical inspection. As a result of our study, the solution we propose is EB inspection using Projection Electron Microscope (PEM) technique and an image acquisition technique to acquire inspection images with Time Delay Integration (TDI) sensor while the stage is continually moving. We have developed an EUV mask inspection tool, EBeyeM, whole design concept includes these techniques. EBeyeM for 2X nm technology node has the following targets, for inspection sensitivity, defects whose size is 20 nm must be detected and, for throughput, inspection time for particle and pattern inspection mode must be less than 2 hours and 13 hours in 100 mm square, respectively. Performance of the proto-type EBeyeM was reported. EBeyeM for 2X nm technology node was remodeled in light of the correlation between Signal to Noise Ratio (SNR) and defect sensitivity for the proto-type EBeyeM. The principal remodeling points were increase of the number of incident electrons to TDI sensor by increasing beam current for illuminating optics and realization of smaller pixel size for imaging optics. This report presents the performance of the remodeled EBeyeM (=EBeyeM for 2X nm) and compares it with that of the proto-type EBeyeM. Performances of image quality, inspection sensitivity and throughput reveal that the EBeyeM for 2X nm is improved. The current performance of the EBeyeM for 2X nm is inspection sensitivity of 20 nm order for both pattern and particle inspection mode, and throughput is 2 hours in 100 mm square for particle inspection mode.

A study of radiation damage in SiN and SiC mask membranes

Radiation damage in SiN and SiC films prepared by low‐pressure chemical vapor deposition (LPCVD) is reported. A pattern placement error of 0.05 μm at the edge of the x‐ray radiation area was introduced for SiN membranes by a radiation dose of 12 kJ/cm2. The electron spin resonance (ESR) signals with a g value of 2.004, which was attributed to the Si–N dangling bond, were observed. Both the error and the spin density increased with increasing radiation dose up to 12 kJ/cm2 and remained constant thereafter. The error was explained as the result of Si–N bond scission caused by x‐ray radiation, leading to tensile stress relaxation in the radiated area. In the case of SiC films, a pattern placement error was less than a detection limit of 0.03 μm for a radiation dose of 10 kJ/cm2. ESR signals with a g value of 2.003, being attributed to the Si–C dangling bond, were observed. However, the spin density in this case did not change by radiation up to 20 kJ/cm2. It is inferred that the LPCVD SiC membrane is damage ...

High performance mask fabrication process for the next-generation mask production

ArF immersion lithography combined with double patterning has been used for fabricating below half pitch 40nm devices. However, when pattern size shrinks below 20nm, we must use new technology like quadruple patterning process or next generation lithography (NGL) solutions. Moreover, with change in lithography tool, next generation mask production will be needed. According to ITRS 2013, fabrication of finer patterns less than 15nm will be required on mask plate in NGL mask production 5 years later [1]. In order to fabricate finer patterns on mask, higher resolution EB mask writer and high performance fabrication process will be required. In a previous study, we investigated a potential of mask fabrication process for finer patterning and achieved 17nm dense line pattern on mask plate by using VSB (Variable Shaped Beam) type EB mask writer and chemically amplified resist [2][3]. After a further investigation, we constructed higher performance mask process by using new EB mask writer EBM9000. EBM9000 is the equipment supporting hp16nm generations photomask production and has high accuracy and high throughput. As a result, we achieved 15.5nm pattern on mask with high productivity. Moreover, from evaluation of isolated pattern, we proved that current mask process has the capability for sub-10nm pattern. These results show that the performance of current mask fabrication process have the potential to fabricate the next-generation mask.

Flexible mask specifications

As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing. This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.

An ultra‐low stress tungsten absorber for x‐ray masks

A stress compensation technique for a tungsten (W) absorber for an x‐ray mask has been developed. Tungsten films with a thickness of 500 nm were deposited using the magnetron dc sputtering method in an argon (Ar) working gas at a power of 1 kW. A high film density (18.0 g/cm3) was obtained at a low working gas pressure. Neon (Ne), Ar, krypton (Kr) and silicon (Si) ion implantations were performed with a projection range (Rp) of 50 nm, at doses of 1014–1015 ions/cm2 to modify the absorber stress. The ion implantation reduced the film stress to less than 5×107 dyn/cm2. Ar and Kr implanted film stress stability was less than 5×107 dyn/cm2. Ne and Si implanted film stresses were not stable.

Development of EB inspection system EBeyeM for EUV mask

We are developing new electron beam inspection system, named EBeyeM, which features high speed and high resolution inspection for EUV mask. Because EBeyeM has the projection electron microscope technique, the scan time of EBeyeM is much faster than that of conventional SEM inspection system. We developed prototype of EBeyeM. The aim of prototype system is to prove the concept of EBeyeM and to estimate the specification of system for 2Xnm and 1Xnm EUV mask. In this paper, we describe outline of EBeyeM and performance results of the prototype system. This system has two inspection mode. One is particle inspection and the other is pattern defect inspection. As to the sensitivity of EBeyeM prototype system, the development target is 30nm for the particle inspection mode and 50nm for pattern defect inspection mode. The performance of this system was evaluated. We confirmed the particle inspection mode of the prototype system could detect 30nm PSL(Polystyrene Latex) and the sensitivity was much higher than conventional optical blank inspection system. And we confirmed that the pattern defect sensitivity of the prototype system was around 45nm. It was recognized that both particle inspection mode and pattern defect inspection mode met the development target. It was estimated by the performance results of the prototype system that the specification of EBeyeM would be able to achieve for 2Xnm EUV mask. As to 1Xnm EUV mask, we are considering tool concept to meet the specification.

Proximity Effect Correction For Electron Beam Lithography: Highly Accurate Correction Method

A new formula for proximity effect correction is discussed. The formula is represented by a series expansion. When infinite terms are used, the formula gives accurate optimum correction doses. The correction accuracy of the new formula is evaluated for the worst case scenario and compared with the conventional formula. It is shown that (1) the new formula suppresses correction errors to less than 0.5% for the deposited energy and (2) dimensional errors are less than 4 nm, even if only the first 3 terms are calculated for critical patterns. By using the new formula, the proximity effect correction can be carried out with sufficient accuracy, even for making reticles of 1 Gbit or higher-capacity DRAMs.

Mask pattern quality assurance based on lithography simulation with fine pixel SEM image

We evaluated the accuracy of the simulation based on mask edge extraction for mask pattern quality assurance. Edge extraction data were obtained from SEM images by use of TOPCON UR-6080 in which high resolution (pixel size of 2nm) and fine pixel SEM image (8000 x 8000 pixels) acquisition is possible. The repeatability of the edge extraction and its impact on wafer image simulation were studied for a normal 1D CD prediction and an edge placement error prediction. The reliability of the simulation was studied by comparing with actual experimental exposure results with an ArF scanner. In the normal 1D CD prediction, we successfully obtained good repeatability and reliability. In 65nm node, we can predict a wafer CD with the accuracy of less than 1 nm using the simulation based on mask edge extraction. In the edge placement error prediction mode, the simulation accuracy is ~5 nm including edge extraction repeatability and the uncertainty of lithography simulation model. The simulation with edge extraction more accurately predicts the resist pattern at line-end in which the actual mask pattern may be varied from the mask target (CAD) than a conventional simulation in which CAD is used as a mask pattern. This result supports the view that the wafer simulation with edge extraction is useful for mask pattern quality assurance because it can consider actual mask pattern shape.

Mask Distortion Analysis for the Fabrication of 1 GBit Dynamic Random Access Memories by X-Ray Lithography

In order to fabricate 1 Gbit dynamic random access memories, or DRAMs, with 0.15 µm minimum features using X-ray lithography, the total overlay error must be no more than 0.05 µm. We assign 0.03 µm to the budget for mask distortion overlay error, which can be subdivided into fabrication-process-induced distortion (0.024 µm), fixturing-induced distortion (0.01 µm), and X-ray exposure-induced distortion (0.01 µm). We study, through theoretical models, these sources of distortion. In our mask-making process, a 75-mm-dia., 0.6-mm-thick Si wafer coated with 1-µm-thick SiC is direct-bonded to a 100-mm-dia., 4-mm-thick Si frame. Tungsten absorber is patterned on the SiC film, and then the wafer is back-etched to form the membrane window. The mask frame opening is used as the back-etching mask. We found that in order to meet the budget for the fabrication-process-induced distortion for a 46-mm-dia. SiC membrane (corresponding to the area of two 1 Gbit DRAM chips) and a target membrane stress of 1 × 109 dyn/cm2, the nonuniformity in the membrane stress or thickness must be under 2 % and the absorber stress no more than 5 × 107 dyn/cm2. High X-ray exposure power leads to a temperature rise of the mask. We found that as long as the X-ray exposures are performed in helium, the distortion in the printed image is within budget, even at high exposure intensities (340 mW/cm2 absorbed power). We also determine that a properly designed three-point mask-holding fixture is sufficient to meet the budget for fixturing induced distortion.