Osamu Tsuchiya

Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability

As the cell size of flash memories is scaled down, the reading error due to threshold voltage (Vth) interference has become a more serious problem, particularly in the case of multi-level-cell (MLC) flash memories, it is necessary for the Vth distribution to be narrower than that of the single-level-cell (SLC). In this work, we propose an advanced air gap structure and process to reduce the interference due to the capacitance between floating gate and floating gate. By applying an air gap between neighboring floating gates as a lowest-dielectric-constant material, we can suppress Vth interference markedly. In addition, we clarified the correlation between the air gap forming process and the memory cell reliability. Hydrogen included in the SiO2 film, which is deposited by plasma-enhanced chemical vapor deposition (CVD) during air gap formation causes the degradation of memory cell endurance and the de-trapping characteristics. We were able to achieve a high-reliability memory cell by reducing the hydrogen concentration in the SiO2 by optimizing the deposition process for air gap formation.