Osamu Yamashiro
Hitachi
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Publication
Featured researches published by Osamu Yamashiro.
design automation conference | 1984
Tsuyoshi Takahashi; Satoshi Kojima; Osamu Yamashiro; Kazuhiko Eguchi; Hideki Fukuda
A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.
Archive | 1992
Munehiro Ogawa; Masato Iwabuchi; Hitoshi Sugihara; Saburo Hojo; Masami Kinoshita; Osamu Yamashiro; Goichi Yokomizo; Mikako Miyama
Archive | 1983
Kanji Yoh; Osamu Yamashiro; Satoshi Meguro
Archive | 1976
Isamu Kobayashi; Osamu Yamashiro; Naoki Yashiki; Tadashi Funakubo
Archive | 1981
Osamu Yamashiro; Toyohiko Hongo
Archive | 1977
Osamu Yamashiro
Archive | 1987
Kanji Yoh; Osamu Yamashiro; Satoshi Meguro; Koichi Nagasawa; Kotaro Nishimura; Harumi Wakimoto; Kazutaka Narita
Archive | 1980
Osamu Yamashiro
Archive | 1978
Osamu Yamashiro
Archive | 1980
Osamu Yamashiro
