Satoshi Meguro

A flash-erase EEPROM cell with an asymmetric source and drain structure

A flash-erase EEPROM cell which consists of a single floating gate transistor is described. The cell is based on self-aligned double polysilicon stacked gate structure without a select transistor. It is programmed and erased by hot electrons at the drain edge similar to a UV-EPROM, and by Fowler-Nordheim tunneling of electrons from the floating gate to the source, respectively. An asymmetry in source and drain regions is introduced to enable fast program/erase operation. In addition, an n+concentration in the source region is optimized to achieve reproducible erasure, which is indispensable to avoid over-erasing problem. The optimized cell enables an erasing time of less than one millisecond with 12. 5 V on the source, and a scatter of erased Vth is almost negligible. Endurance and data retention characteristics is also adequate for implementation in memory chips. The small cell area of 9.3µm2is accomplished in a 0.8µm technology.

A polysilicon transistor technology for large capacity SRAMs

A polysilicon PMOS cell technology is discussed. Bottom-gated polysilicon PMOS transistors are stacked over NMOS transistors, and a 17 mu m/sup 2/ cell size is realized with a 0.6 mu m design rule. In order to achieve high-performance polysilicon PMOS, both gate oxide and channel polysilicon thicknesses of the PMOS are reduced to 40 nm. A 0.4 mu m length gate-to-drain offset structure is adopted. Moreover, two novel approaches to O/sub 2/ plasma treatment prior to metal H/sub 2/-N/sub 2/ anneal and oxidation of channel polysilicon have been found to be effective for achieving excellent polysilicon PMOS characteristics. As a result, polysilicon PMOS which has a 25 fA off-current (V/sub d/=-5 V, V/sub g/=0 V) and a 0.1 nA on-current (V/sub d/=-5 V, V/sub g/=-2 V) has been realized.<<ETX>>

Hot carrier degradation modes and optimization of LDD MOSFETs

The hot carrier instability and the related device characteristics of Leff= 1µm MOSFETs with Lightly Doped Drain (LDD) structure is evaluated in detail. For the n- dose below 1E13/cm2, a new type of IBB and IG increase was found when the gate bias, VG, was increased toward and over the drain bias, VD, and related new modes of hot carrier instability were confirmed. The instability for the lower VG stress is attributed to the charge build-up at the n- drain region, while the instability for the larger VG stress is attributed to the oxide degradation at both source and drain regions. The device characteristics and the mechanism of instability for n→= 1E13/cm2 are similar to those of conventional devices. It is shown that the instability inherent to the LDD structure can be suppressed by optimizing the n-dose. Thereby, it is important that the lateral electric field peak remains under the gate.

A 15ns 1mb Cmos Sram

ing of 512 rows and 64 columns and controlled by a word decoder. One word line is selected by a word decoder according to the selection signal from a pre-word-decoder. A high-speed word decoder is essential for fast access in this architecture. Figure 2 shows the circuit schematic of two word decoders using 8 PMOS-load NAND gates with a common lower stage NMOS. This has two advantages. First, the gate capacitances of the decoders connected to signal lines are reduced substantially, so that signal propagation delay is greatly decreased. Second, the number of PMOS and NMOS in NAND gates can be drastically reduced permitting a decoder width of 6 6 ~ . This is especially significant because the chip has 32 sets of word decoders. The same architecture is used for other decoders, including column and pre-word. This procedure contributes to achieving small chip size and fast access time. A sense amplifier design with three-stage dynamic gain is shown in Figure 3. Here, common data bus signals are amplified by two stages of paired current, mirror amplifiers and are transferred to the main data bus through transfer gates. Therefore, the main data bus is driven directly by the second stage of the sense amplifiers. The main data bus signals cannot rapidly reach large amplitudes because of the large stray capacitance of the main data bus, and must be amplified by a main amplifier located close to an output buffer. The gains of those amplifiers are dynamically controlled by switching the current using Address Transition Detector (ATD) pulses. This allows high sense speed with reduced average current.

A 256K CMOS SRAM with variable impedance data-line loads

A 256K (32K/spl times/8) CMOS SRAM utilizing variable impedance loads and a pulsed word-line (PWL) technique is described. In the WRITE cycle, the variable impedance loads of the data lines enter a high impedance state and reduce the operating power. During the READ cycle, the PWL technique is used to achieve high-speed operation and low power dissipation. The internal clocks generated by the address transition detectors activate word-line and sense amplifiers for READ operation and disable them after the data are sent to D/SUB out/ buffers. This PWL technique eliminates the precharge time of 20 ns, which corresponds to 30% of the access time. The RAM offers 45-ns address access time and 40-mW operating power in the WRITE cycle of 1 MHz.

A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two separate gate formations. A pair of split word-lines is stacked over pull-down transistors. That permits large cell ratio in small cell area and independent optimization of pull-down and access transistors. Threshold voltage of access transistors is lowered to improve cell stability. Top gate thin film polysilicon transistor and Vcc plate are used to make cell node capacitor and improve soft error immunity. This technology is applied to a fast 16M bit SRAM and enabled a 7.16 /spl mu/m/sup 2/ cell area in relaxed 0.4 /spl mu/m layout rule utilizing conventional i-line stepper without phase-shift masks.<<ETX>>

A 256K CMOS SRAM with variable-impedance loads

A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm2memory cell.

Hi-CMOS III technology

Hi-CMOS III (1.3µm CMOS) technology is described. The basic approach is the 2/3 scaling of Hi-CMOS II (2µm CMOS) with constant voltage. Lightly Doped Drain (LDD) NMOS, and newly developed Buried Channel Lightly Doped Drain (BCLDD) PMOS, with polycide gate are adopted to reduce short channel effects and delays in interconnection lines. Both NMOS and PMOS can be used at the gate length of 1.2µm. Spacers for LDD and tapered contact holes have improved the coverage of aluminum layer significantly. Also post-contact-doping is adopted to allow the overlap of contact holes and diffusion edges, and to reduce contact resistance. These process integration result in simple and high performance Hi-CMOS III technology.

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current

A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current (V/sub cc/=3 V) with a 17- mu m/sup 2/ memory cell area. A 122-mm/sup 2/ (7.2*16.9-mm) chip is achieved by the double-array word-decoder architecture.<<ETX>>

A high performance memory cell technology for mega bit EPROMS

A high performance memory cell technology for mega bit EPROMs has been developed using 1.3 µm process. Deeply Doped Channel ( DDC ) and Double Step Drain ( DSD ) structures incorporated into the scaled memory cell improve programming speeds by more than one order of magnitude with maintaining high breakdown voltages, small parasitic effects,and soft-write immunity. This technology has been successfully applied to one mega bit CMOS EPROMs with a cell size of 19.27 µm2and realized programming time less than 10 µs for a programming voltage of 12.5 V.