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A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution particularly aimed at a low-clock rate implementation. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module in the device for half-duplex operation. The results from this paper enable the baseband designers of the 200 Mbit/sec variant of multiband UWB systems (and indeed other OFDM based receivers) using system-on-chip (SoC), FPGA and ASIC technology to create cost effective and low power consumer electronics product solutions biased toward the very competitive market.

Power performance with gated clocks of a pipelined Cordic core

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops are used when synthesized with FPGA logic resources.

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits.

A double data rate architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

A Practical Low Cost Architecture for a MB-OFDM Equalizer (ECMA-368)

The relative fast processing speed requirements in wireless personal area network (WPAN) consumer based products are often in conflict with their low power and cost requirements. In order to solve this conflict the efficiency and cost effectiveness of these products and the underlying functional modules become paramount. This paper presents a low-cost, simple, yet high performance solution for the receiver channel estimator and equalizer for the mutiband OFDM (MB-OFDM) system, particularly directed to the WiMedia Consortium Physical Later (ECMA-368) consumer implementation for wireless-USB and fast Bluetooth. In this paper, the receiver fixed point performance is measured and the results indicate excellent performance compared to the current literature.

Pipelining considerations for an FPGA case

This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.

A new organization for a perceptron-based branch predictor and its FPGA implementation

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

TCL/TK for EDA Tools

Tcl/Tk scripting language has become the de-facto standard for EDA tools. This paper explains how to start working with Tcl/Tk using simple examples. Two complete applications are presented to show in more detail the capabilities of the language. In one script average power consumption of a digital system is automated. A second script creates a virtual display driven by the simulation of a graphic card.

Generic construction of monitors for Floating Point Unit designs

This paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.