Robert Simon Sherratt

A Survey on Wireless Body Area Networks for eHealthcare Systems in Residential Environments

Current progress in wearable and implanted health monitoring technologies has strong potential to alter the future of healthcare services by enabling ubiquitous monitoring of patients. A typical health monitoring system consists of a network of wearable or implanted sensors that constantly monitor physiological parameters. Collected data are relayed using existing wireless communication protocols to a base station for additional processing. This article provides researchers with information to compare the existing low-power communication technologies that can potentially support the rapid development and deployment of WBAN systems, and mainly focuses on remote monitoring of elderly or chronically ill patients in residential environments.

Numerical precision requirements on the multiband ultra-wideband system for practical consumer electronic devices

This paper discusses the requirements on the numerical precision for a practical multiband ultra-wideband (UWB) consumer electronic solution. To this end, we first present the possibilities that UWB has to offer to the consumer electronics market and the possible range of devices. We then show the performance of a model of the UWB baseband system implemented using floating point precision. Then, by simulation we find the minimal numerical precision required to maintain floating-point performance for each of the specific data types and signals present in the UWB baseband. Finally, we present a full description of the numerical requirements for both the transmit and receive components of the UWB baseband. The numerical precision results obtained in this paper can then be used by baseband designers to implement cost effective UWB systems using system-on-chip (SoC), FPGA and ASIC technology solutions biased toward the competitive consumer electronics market.

Enhancing MB-OFDM throughput with dual circular 32-QAM

Quadrature phase shift keying (QPSK) and dual carrier modulation (DCM) are currently used as the modulation schemes for multiband orthogonal frequency division multiplexing (MB-OFDM) in the ECMA-368 defined ultra-wideband (UWB) radio platform. ECMA-368 has been chosen as the physical radio platform for many systems including wireless USB (W-USB), Bluetooth 3.0 and wireless HDMI; hence ECMA-368 is an important issue to consumer electronics and the users experience of these products. To enable the transport of high-rate USB, ECMA-368 offers up to 480 Mb/s instantaneous bit rate to the medium access control (MAC) layer, but depending on radio channel conditions dropped packets unfortunately result in a lower throughput. This paper presents an alternative high data rate modulation scheme that fits within the configuration of the current standard increasing system throughput by achieving 600 Mb/s (reliable to 3.1 meters) thus maintaining the high rate USB throughput even with a moderate level of dropped packets. The modulation system is termed dual circular 32-QAM (DC 32-QAM). The system performance for DC 32-QAM modulation is presented and compared with 16-QAM and DCM.

A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution particularly aimed at a low-clock rate implementation. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module in the device for half-duplex operation. The results from this paper enable the baseband designers of the 200 Mbit/sec variant of multiband UWB systems (and indeed other OFDM based receivers) using system-on-chip (SoC), FPGA and ASIC technology to create cost effective and low power consumer electronics product solutions biased toward the very competitive market.

Analysis of a DVB-T compliant receiver simulation under various multipath conditions

Since 1966, coded orthogonal frequency division multiplexing (COFDM) has been investigated to determine the possibility of reducing the overall throughput of a digitally modulated terrestrial television channel. In the investigations, many assumptions have emerged. One common misconception is that in a terrestrial environment, COFDM has an inherent immunity to multipath interference. A theoretical analysis of a multipath channel, along with simulation results has shown that this assumption does not hold the information is considered when including the radio frequency modulation and demodulation. This paper presents a background into the inception of COFDM, a mathematical analysis of the digitally modulated television signal under multipath conditions and the results of a European Digital Video Broadcasting-Terrestrial (DVB-T) compliant simulation model with MPEG-2 bitstreams transmitted under various multipath conditions.

Parallel pipelined array architectures for real-time histogram computation in consumer devices

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle 1.

A dual QPSK soft-demapper for multiband OFDM exploiting time-domain spreading and guard interval diversity

When considering the relative fast processing speeds and low power requirements for wireless personal area networks (WPAN) including wireless universal serial bus (WUSB) consumer based products, then the efficiency and cost effectiveness of these products become paramount. This paper presents an improved soft-output QPSK demapper suitable for the products above that not only exploits time diversity and guard carrier diversity, but also merges the demapping and symbol combining functions together to minimize CPU cycles, or memory access dependant upon the chosen implementation architecture. The proposed demapper is presented in the context of multiband OFDM version of ultra wideband (UWB) (ECMA-368) as the chosen physical implementation for high-rate wireless USB.

A double data rate architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

A Practical Low Cost Architecture for a MB-OFDM Equalizer (ECMA-368)

The relative fast processing speed requirements in wireless personal area network (WPAN) consumer based products are often in conflict with their low power and cost requirements. In order to solve this conflict the efficiency and cost effectiveness of these products and the underlying functional modules become paramount. This paper presents a low-cost, simple, yet high performance solution for the receiver channel estimator and equalizer for the mutiband OFDM (MB-OFDM) system, particularly directed to the WiMedia Consortium Physical Later (ECMA-368) consumer implementation for wireless-USB and fast Bluetooth. In this paper, the receiver fixed point performance is measured and the results indicate excellent performance compared to the current literature.

Performance and conformance results of the deterministic DVB-T equalizer

One of the enablers for new consumer electronics based products to be accepted in to the market is the availability of inexpensive, flexible and multi-standard chipsets and services. DVB-T, the principal standard for terrestrial broadcast of digital video in Europe, has been extremely successful in leading to governments reconsidering their targets for analogue television broadcast switch-off. To enable one further small step in creating increasingly cost effective chipsets, the OFDM deterministic equalizer has been presented before with its application to DVB-T. This paper discusses the test set-up of a DVB-T compliant baseband simulation that includes the deterministic equalizer and DVB-T standard propagation channels. This is then followed by a presentation of the found inner and outer bit error rate (BER) results using various modulation levels, coding rates and propagation channels in order to ascertain the actual performance of the deterministic equalizer.