Oswin Ehrmann

High aspect ratio TSV copper filling with different seed layers

The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation was performed for reliability assessment.

Fabrication of Application Specific Integrated Passive Devices Using Wafer Level Packaging Technologies

Integrated passives have become increasingly popular in recent years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context, particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). IPDs combine different passive components (R,L ,C ) in one subcomponent to be assembled in one step by standard technologies like surface mount device (SMD) or flip chip. In this paper, the wafer level thin film fabrication of integrated passive devices (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization, as well as results from the electrical characterization will be discussed.

Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging

Wafer Level Packaging has the highest potential for future single chip packages. The package is completed directly on the wafer then singulated by dicing for the assembly in a flip chip fashion. All packaging and testing operations of simulated dice will be replaced by whole wafer fabrication and wafer level testing. The result is a technology which leads the way to Fab Integrated Packaging (FIP). An evaluation of the reliability of a new Wafer-Level Chip Scale Package (WL-CSP) was done in the FIP program, a joint development program between Fraunhofer IZM and Motorola. As a CSP the FIP-CSP eliminates underfill operation during flip-chip bonding using high through-put SMT assembly lines. The technological structure of this FIP-CSP is a pad redistributed die with a solder ball array. A stress compensation layer (SCL) embeds the solder balls before second solder balls are stencil printed or placed on top of embedded balls. The reliability of this wafer-level CSP presented here was simulated and evaluated by test samples. The test chip was a 1 cm/spl times/1 cm square chip which was redistributed to an 14/spl times/14 ball array with a pitch of 0.5 mm. JEDEC Level 3, 1000 cycles AATC (-55/spl deg/C/+125/spl deg/C) and 48 h Autoclave on component level were passed. On board level 1000 hours humidity storage at 85/spl deg/C (85/85 test) and 1000 cycles -55/+125/spl deg/C were passed.

TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as intermediate carrier and wiring device for IC components like logics, memories and sensors. Due to custom specific front and back side wiring interposers enable to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. High density copper filled TSVs with high aspect ratio as well as high density multi layer wiring using electro plated copper as conductive material and low loss dielectrics enable high performance signal transmission at interposer level without serious losses by parasitic effects. This paper presents the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer level assembly with IC components. Special focus is drawn on the TSV formation process including via etching, isolation and filling as well as front side high density wiring and subsequent backside processing of the thin TSV wafers. In this context, also temporary wafer to wafer bonding which is required for backside processing of thin TSV wafers is discussed. The final interposers which carry one or more IC components have lateral dimensions up to several square centimeters and thicknesses between 50–100 μm. They include up to several thousands of TSVs per device with a single electrical resistance between 4.9–5.7 mOhms. All processes were run using production equipment at 200 mm wafers.

Thin film integration of passives - single components, filters, integrated passive devices

The increasing demands on future electronic products require more efficient system integration technologies. Especially the package density gap at board level with the high integrated circuits (ICs) on the one hand and the discrete passive components on the other has to be closed by new packaging technologies which integrate the passive components into the substrate, an interposer or the IC itself. This paper presents investigations for the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB). Technologies from wafer level packaging were adapted for manufacturing of the integrated components. The examinations were carried out with special focus on integrated coils and passive filter structures. Build up, design, processing as well as results of the electrical characterization of the integrated components are described in detail. Furthermore, an integrated passive device (IPD) for application as a filter element in the Bluetooth band is presented.

Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration

In this paper we describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing. Thin wafer handling is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures. The work was done as evaluation study to prove the compatibility of a thin wafer handling system with standard processes used for thinning and backside processing of “via-first” TSV wafers as well as for thinning of bumped wafers. The used thin wafer handling system is based on perforated carrier wafers, which are bonded by an adhesive to the customer wafer and de-bonded by solvent release of the adhesive. All wafers used in this work had 200 mm format. The evaluation was run systematically in three major phases. In the first phase the main process scenarios, which require thin wafer handling, were defined. In a second phase setup trials for bonding, thinning, backside processing and de-bonding were run on monitor wafers with different types of front side topography, but without TSVs. After finishing the setup trials in a third phase, the monitor wafers were replaced by wafers with copper filled TSVs, which were fabricated in “via-first” technology. Using the established thin wafer handling and processing sequence, silicon interposer wafers with 55 μm thickness were manufactured. The measured via chains have via pitches of 28 μm using 15 μm via diameter.

Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling

Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integration. In this context we introduce the polyimide material HD3007 which is suitable for temporary bonding of silicon wafers to carrier wafers by using a thermo compression process. Coating and bonding processes for 200 mm and 150 mm wafers with and without topography as well as two de-bonding concepts which are based on laser assisted and solvent assisted release processes are presented. Based on tests with temporary bonded 200 mm wafers, we found a very high compatibility of the bonded compound wafers with standard WLP process equipment and work flows suitable for backside processing of “via first” TSV wafers. Processes like silicon back grinding to a remaining thickness of 60 μm, dry etching, wet etching, CMP, PVD, spin coating of resists and polymers, lithography, electro plating and polymer curing were evaluated and are described in detail. Even at high temperatures up to 300°C and vacuum levels up to 10-4 mbar, the temporary bond layer was stable and no delamination occurred. 60 μm thin wafers could be processed and de-bonded without any problems using both release methods. De-bonding times of less than a couple minutes can be realized with laser assisted de-bonding and several minutes with a solvent based release. Compared to glues of other temporary handling systems, the proposed material offers the highest temperature budget for thin wafer backside processing as well as fast and easy de-bonding at room temperature.

Characteristics of fritting contacts utilized for micromachined wafer probe cards

We have investigated the relationship between contact forces and the fritting which should be utilized for making contact to integrated circuit pads in micromachined wafer probe cards. Micromachined probe cards are requisite to tests of higher pad-density and smaller pad-pitch chips with high-speed signals above 1 GHz. In addition, if a microactuator is integrated into each probe, we can realize a novel probe card in which contacts can directly be switched on and off. The critical problem of the micromachined probe cards, however, is that each micromachined probe cannot generate or endure the force required to break the oxide on an Al pad surface mechanically. To overcome the problem, we planned to reduce the required contact force by putting the fritting effect to good use. For that, in this article, we have measured forces required for making contact to Al pads and contact resistance when utilizing the fritting process for the break of the pad surface oxide. Furthermore, we have also measured the force ...

Biocompatible hybrid flip chip microsystem integration for next generation wireless neural interfaces

Chronically implantable, wireless neural interfaces require biocompatible, long term stable, and high density integration of all functional sub-components. For this, the integration and interconnection concept of the wireless neural interface was proposed and interconnection materials and methods were investigated and characterized. The module consists of an electronics IC assembled to an electrode array. Thin film flex coils are glued onto the back side of the IC. The IC was interconnected by AuSn reflow flip chip bonding on the backside of the Utah electrode array (UEA) and off-chip electric components were SnCu0.7 soldered on the integrated IC/UEA module to guarantee a reliable connectivity

Embedding technology-a chip-first approach using BCB

With the current trend to ever faster clock rates the propagation delays between the chips constitute a significant portion of the clock cycle. Mounting both active and passive devices as closely together as possible will therefore boost systems performance. Although flip-chipped devices have good performance, design constraints may prevent the placement of pads to comply with flip chip design rules. An additional advantage of the embedding technology is the possibility to employ 3-D stacking, the highest package density. Bare dice and standard passive components were embedded into a ceramic substrate to achieve a common, planar surface. Hence by employing thin-film processing all components can be directly interconnected to the copper routing of the module. Benzocylobutene (BCB) with its low curing temperature is preferred as dielectrical polymer for the embedding technology. Application of bonding or soldering techniques which might limit the reliability is avoided. This offers excellent electrical properties of the wiring system. By planarizing the reverse side of the MCM a low thermal resistance between heat sink and dice can be accomplished simultaneously for all embedded components. An SRAM MCM and a Thermotest MCM demonstrate the facibility of the embedding technology.