Herbert Reichl

Fatigue life models for SnAgCu and SnPb solder joints evaluated by experiments and simulation

In recent years, many solder fatigue models have been developed to predict the fatigue life of solder joints under thermal cycle conditions. While a variety of life prediction models have been proposed for near eutectic SnPb(Ag)-solder joints in the literature, not enough work has been reported in extending these models to lead-free soldered assemblies. The development of lie prediction models requires a deep insight into failure modes, constitutive models for the themnomechanical behavior of solders and an experimental reliability database. This is needed for the correlation of experimentally determined cycles-to-failure to simulation results by fmiteelement analysis. This paper describes in detail the life-prediction models of SnPh(Ag) and SnAgCu solder joints for thermal cycle conditions. To obtain reliable FEM input and to verify simulation results, a variety of material testing and experimental fatigue data is necessary. The accuracy of lieprediction tools has also become critically important, as the designs need to he evaluated and improved with a high degree of reliability, not through relative comparison but by providing absolute numbers. This work deals with the effect of different solder interconnect alloys (Sn59Pb40Agl and Sn95.5Ag3.8Cu0.7) and the effect of different package types (PBGAs, CSPs, Flip Chip on FR-4 with and without underfill) on the fatigue life. Different temperature cycling conditions are applied.

Sustainability in manufacturing: Recovery of resources in product and material cycles

Global Framework.- Life Cycle Engineering and Management.- Product Development.- Processes and Tools for Disassembly.- Planning for Remanufacturing and Recycling.- Enabling for Sustainability in Engineering.- Roadmap.

Through silicon via technology — processes and reliability for wafer-level 3D system integration

3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.

High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes

Through-silicon vias (TSVs) in low, medium and high resistivity silicon for 3-D chip integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 GHz, considering the slow-wave, dielectric quasi-TEM and skin-effect modes. The frequency ranges of these modes and their transitions are predicted using resistivity-frequency domain charts. The impact of the modes on signal integrity is quantified, and three coaxial TSV configurations are proposed to minimize this impact. Finally, conventional expressions for calculating the per-unit-length circuit parameters of transmission lines are extended and used to analytically capture the frequency dependent behavior of TSVs, considering the impact of the mixed dielectric (silicon dioxide-silicon-silicon dioxide) around the TSVs. Excellent correlation is obtained between the analytical calculations using the extended expressions and electromagnetic field simulations up to 130 GHz. These extended expressions can be implemented directly in electronic design automation tools to facilitate performance evaluation of TSVs, prior to system design.

Forced convective interlayer cooling in vertically integrated packages

The heat removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters les 200 mum. An experimental investigation with uniform and double-side heat flux at Reynolds numbers les 1000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. Parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mum and fluid structure heights of 100 to 200 mum were tested. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin inline structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks with a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 mum interconnect pitch to <100 W/cm2 at 4 cm2.

High aspect ratio TSV copper filling with different seed layers

The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation was performed for reliability assessment.

Role of Cu in dissolution kinetics of Cu metallization in molten Sn-based solders

The focus of this study is on the role of Cu content in the dissolution kinetics of Cu in high-Sn solders during the solid/liquid reaction accompanied by interfacial intermetallic compound formation. Small additions of Cu (0.7%, 1.5%) in high-Sn solders dramatically decrease the dissolution rate of Cu at low temperatures. Sn-3.5Ag, as expected, has a dissolution rate similar to that of pure Sn. The difference in dissolution rate of Cu in various molten solders is explained in terms of the solubility limit of Cu in molten solders based on the Cu-Sn phase diagram. The correlation between the metallurgical aspects of interfacial η(Cu6Sn5) phase formation and dissolution kinetics of Cu in molten solders leads to an understanding of the mechanism that controls the dissolution rate of Cu in molten solders.

Fabrication of high depth-to-width aspect ratio microstructures

It is reported that a 3-D fabrication process, based on sputtering of a thin-film plating base, on conventional UV lithography, and on electrochemical deposition of gold, makes microstructures of considerable height and resolution possible. The thin-film formation and the lithographic process are outlined, particular attention being paid to layer deposition and structure printing. The present resolution limit is about 4.5 mu m for a 30- mu m-thick resist. Much thicker layers (80 mu m) can be printed with reduced resolution. The results are discussed and process characteristics relevant in various applications are considered.<<ETX>>

3-D Thin film interposer based on TGV (Through Glass Vias): An alternative to Si-interposer

Interposers for SiP will become more and more important for advanced electronic systems. But through substrate vias are essential for the 3-D integration. Being a standard for laminate based materials this is much more complex for Si-wafers: High speed etching has to be combined with complex electrical isolation, diffusion barriers and void-free Cu-filling. Without doubt this can be solved in lab-scale but for high production scale cost is a tremendous barrier. Glass wafers with W-plugs have been intensively investigated in this paper. A new acronym has been posted to high-light this technology: TGV for Through Glass Vias. The results of modeling and simulation of TGV at RF/Microwave frequencies showed a very good compromise between wafer thickness, TGV-shape and via diameter for vertical metal plugs with 100 μm diameters in 500 μm thick glass wafer still very stable for thin film wafer processing without costly temporary wafer bonding processes. Therefore the HermeS® from Schott was chosen as the basis for a prototype of a bidirectional 4 × 10 Gbps electro-optical transceiver module. Thin film RDL and bumping of these wafers was possible without any modifications to Si-wafer. First thermal cycles showed very promising results for the reliability of this concept.

Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology

This paper presents a flip chip technology based on an electroless Ni/Au bumping process which has been developed by IZM/TUB. Nickel bumps offer a surface with very good suitability for flip chip soldering. In the following an interconnection method is described which uses ultra fine pitch stencil printing of solder paste on wafers, ceramic and organic substrates. The eutectic Pb/Sn solder alloy is by far the most commonly used solder in industry. Facing the ecological challenge and federal legislation the paste suppliers are developing lead free solder pastes. Due to the fact that the variety of solder pastes is still growing it is necessary to find an ideal alloy for a specific application. Therefore, in comparison to eutectic Sn/Pb solder different alloys, e.g. Bi/Sn, Sn/Bi/Cu, Sn/Ag, Sn/Cu, Au/Sn are investigated in this paper. In the first part of this paper a low cost flip chip technology based on chemical Ni/Au bumping and solder printing is presented. For this the basic process steps and key aspects are described in detail. The experimental results of an ultra fine pitch technique on wafers and on substrates are shown as well. The second part of this paper presents a comparison of the properties of different solder pastes concerning the usability for flip chip technology. For this, flip chip soldering using dies with Ni/Au bumps was performed on ceramic and FR-4 substrates. The quality of the flip chip joints were investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling are presented. A comparison of underfilled and nonunderfilled flip chip devices will complete the investigations.