Otto Manck

Depth Resolution Enhancement Technique for CMOS Time-of-Flight 3-D Image Sensors

Introducing Time-of-Flight 3-D image sensors to actual engineering applications, such as pattern recognition, is constrained not only by their limited depth and lateral resolution, but also by how similar the precision of depth measurement throughout the whole pixel-matrix is. In real operating environment, an observed 3-D-scene hardly exhibits a homogeneous reflectance factor. Moreover, the light-beam (laser source) presents a nonuniform optical power distribution in space. Thus, the amount of the incident light on the sensor surface varies drastically from one pixel to another, and so does the signal-to-noise ratio. To address this problem, this paper investigates the impact of both scene and light-source non-ideal characteristics on the sensor performance. An adaptive on-pixel analog signal processing technique is also presented and applied to the design of a 32 × 32 complementary metal oxide semiconductor (CMOS) range camera, featuring an interesting cost-efficient solution.

On the Capability of Artificial Neural Networks to Compensate Nonlinearities in Wavelength Sensing

An intelligent sensor for light wavelength readout, suitable for visible range optical applications, has been developed. Using buried triple photo-junction as basic pixel sensing element in combination with artificial neural network (ANN), the wavelength readout with a full-scale error of less than 1.5% over the range of 400 to 780 nm can be achieved. Through this work, the applicability of the ANN approach in optical sensing is investigated and compared with conventional methods, and a good compromise between accuracy and the possibility for on-chip implementation was thus found. Indeed, this technique can serve different purposes and may replace conventional methods.

7.72 ppm/°C, ultralow power, high PSRR CMOS bandgap reference voltage

This paper describes a CMOS bandgap reference fabricated in 0.18μm TSMC CMOS technology, with ultralow power consumption, high Power Supply Rejection Ratio (PSRR) and less temperature drift over wide temperature range. This is achieved by using a straightforward 3 bits trimming circuit design includes high ohmic polysilicon unit resistors to save area and 8 to 1 multiplexer digitally controlled to switch between the 8 different outputs. The performance of the design was verified experimentally. The implemented bandgap reference voltage measured has showed a temperature coefficient of 7.72 ppm/°C over temperature range of -40°C to 125°C on wide supply voltage from 2.6V to 4V and consumes a supply current of 1.054μA at 4V, PSRR of -62dB at 1GHz are easily achieved, which make it widely applicable in portable equipment. The active area of the circuit is 0.1 mm2.

An Enhanced Technique for Ultrasonic Flow Metering Featuring Very Low Jitter and Offset

This paper proposes a new, improved method for water flow metering. It applies to a transit time ultrasonic flow meter device. In principle, the flow of a given liquid in a pipe is obtained by measuring the transit times of an ultrasonic wave in the upstream and downstream directions. The difference between these times is, in theory, linearly proportional to the liquid flow velocity. However, the fainter the flow is, the smaller the transit time difference (TTD) is. This difference can be as low as a few picoseconds, which gives rise to many technical difficulties in measuring such a small time difference with a given accuracy. The proposed method relies on measuring the TTD indirectly by computing the phase difference between the steady-state parts of the received signals in the upstream and downstream directions and by using a least-square-sine-fitting technique. This reduces the effect of the jitter noise and the offset, which limit measurement precision at very low flow velocity. The obtained measurement results illustrate the robustness of the proposed method, as we measure the TTD at no-flow conditions, with a precision as low as 10 ps peak-to-peak and a TTD offset of zero, within a temperature range from room temperature to 80 °C. This allows us to reach a smaller minimum detectable flow when compared with previous techniques. The proposed method exhibits a better trade-off between measurement accuracy and system complexity. It can be completely integrated in an ASIC (application specific integrated circuit) or incorporated in a CPU- or micro-controller-based system.

A Programmable Voltage Reference Dsign

The paper emphasizes the circuit innovations of a key analog function realized on the IAD GmbH DLC_2 family chip, a precision programmable voltage reference with superior performance capabilities dedicated for an integrated 10 bits D/A converter. The chip developed in co-operation of IAD and MAZ Brandenburg has been produced with 0.35 mum CMOS switched capacitor technology from AMS, it can be used on the one hand within typical power-line applications, such us controlling and management, and the other hand for data communication, such as telephony or internet access. The programmable voltage reference is based on a new design that provides fast programmability between voltages and stable voltage operation from 0.25 Vdda to 0.75 Vdda. The main objective is to select a design that meets as close as possible criteria related to the chip specification requirements such as reliability, flexibility, and integration area. Consequently, an adequate programmable voltage reference is proposed which is 4 bits decoder-based converter architecture

In-pixel implementation of an area-efficient analog-signal-processing for CMOS-3D image sensor

The paper presents the design and test of a 32×32 CMOS 3D-image sensor, based-on indirect time-of-flight (ToF) technique with its derived algorithm: MDSI (multiple double short time integration). The design key feature is the implementation, in pixel-level, of analog signal processing; namely: correlated double sampling (CDS) and analog averaging. Which leads to a significant enhancement in term of signal-to-noise ratio (SNR), while keeping reasonable fill-factor and power consumption. The chip has been fabricated using 0.6um standard CMOS process. The overall achieved performances exhibit an interesting trade-off.