Ozgur Ozsun

Study of two-phase pressure drop and heat transfer in a micro-scale pin fin cavity: Part A

Novel hierarchical radially expanding micro-channel networks with pin fins have been proposed recently to enable high-performance embedded two-phase liquid cooling of two- and three-dimensional integrated circuits dissipating extremely high heat fluxes (of the order of 1kW/cm2) [1]. The effective design of such a complex two-phase liquid cooling architecture requires a comprehensive understanding of the various constituent sub-systems. Fundamental experiments were performed as a part of this work to study and model two-phase flow boiling and heat transfer using R-1234ze refrigerant in a two-port micro-scale cavity populated with pin fins which provide structures to accommodate vertical electrical interconnects (TSVs) as well as enhance heat transfer. In this first part of a two-part paper, results from the aforementioned fundamental study are presented. First, experimental procedure, including motivation, test set up, data acquisition and analysis is described. Next, the procedure for data reduction is detailed where an assumption of one-dimensional (1D) heat conduction in silicon is applied to resolve the two-phase flow boiling data. From this reduced data, empirical pressure drop and heat transfer correlations were derived as a function of mass flux, wall heat flux, pin fin angle of attack and the local vapor quality. These correlations were used to simulate and design two-phase cooled microchannels with enhanced heat transfer geometries such as pin fins, using compact low-complexity thermal models called STEAM and RTP. The accuracy and the speed of the models are demonstrated using simulations and validation against the experimental data.

Thermal model for embedded two-phase liquid cooled microprocessor

Chip embedded two phase evaporative cooling is an enabling technology to provide intra-chip cooling of high power chips and interlayer cooling for 3D chip stacks. Utilizing an interconnect-compatible dielectric fluid provides a cooling solution compatible with chip to chip interconnects for future high power 3D chip stacks. However, lack of high fidelity and computationally manageable conjugate thermal models limits the development of this technology. To address that, a thermal model for fast and accurate prediction of thermal and electrical behavior of an embedded two-phase liquid cooled micro-processor module is described in this paper. This model consists of a state-of-the-art conjugate heat transfer model for two-phase flow boiling through chip embedded micron-scale channels and a physics-based empirically tuned electrical model of the microprocessor. Extensive model validation using data from several experiments was performed to quantify the accuracy of this model under different operating conditions (including various chip operating frequencies and coolant mass flow rates). Results showed that this model can predict the electrical behavior as well as two-phase flow and heat transfer characteristics with very good accuracy. Overall, the chip junction temperature predictions were within two degrees of the experimental data and the temperature-dependent chip power predictions were within 10%.

Heat transfer modelling of a dual-side cooled microprocessor chip stack with embedded micro-channels

The thermal management of 3D chip stacks is a limiting factor in dense system integration, due to the increased volumetric power density caused by multilayer thermal interfaces. Hence, novel cooling solutions will be a key driver in realisation of these 3D integrated chip stacks. In this work the performance of a dual-side water cooling system is analysed. A numerical method utilizing porous media approach is applied to extract design rules for the embedded channels within the chip stack.

Microfluidic two-phase cooling of a high power microprocessor part B: Test and characterization

The effective use of embedded radial expanding micro-channels with micro-pin fields for two phase cooling of semiconductor dies has been demonstrated [1, 2]. In this second part of a two part paper, the functional results of integrating this approach into a high performance server are presented. First, a number of microprocessor modules were fully characterized within a high performance server utilizing both an idle state and a workload designed to drive maximum processor power. These characterizations were done across a wide operating frequency range of 2.2 to 4.3 GHz. After modification to incorporate embedded radial expanding micro-channels for two phase flow, the microprocessor modules were reinstalled in the server supported by a two phase liquid cooling pump and condenser system with flow, temperature and pressure drop measuring capabilities. The modules were then characterized again over the same operating frequency range for a range of coolant flow rates and resulting average vapor qualities. The results show full processor function and excellent thermal behavior across a wide range of coolant flow rates, directly demonstrating the feasibility of this technology for cooling actual high power electronic devices.

Microfluidic two-phase cooling of a high power microprocessor part A: Design and fabrication

The effective use of embedded radial expanding micro-channels with micro-pin fields for two phase cooling of a microprocessor die has been demonstrated. In this first part of a two part paper, the integration of this approach into a functional high performance server is presented. Modeling was conducted to design radial micro-channels, micro-pin fields, and orifices to properly distribute flow according to the anticipated maximum work load distribution of power across the processor chip. This design incorporates modeling of two-phase pressure drop under power, allowing for a tight distribution of exit vapor quality across the radial channels. Integrating this technology into a functioning server requires a packaging design and assembly approach compatible with an originally lidded fully functional organic single chip processor module. Processes for de-lidding, channel etching, and packaging for desired coolant flow and thermal behavior through the chip-embedded channels were developed. The resulting processor modules were re-installed in a commercial server and the fluidic performance was measured. In the second part, the functional performance experiments and results are detailed.

Dual-side heat removal by micro-channel cold plate and silicon-interposer with embedded fluid channels

In this study, a dual-side cooling topology based on a silicon cold plate and an electrical functional silicon-interposer with embedded fluid channels is benchmarked against mere back-side cooling. The back-side cold plate can be operated in a split-flow mode, whereas in the case of the interposer only a single in- and outlet can be implemented, which results in a cross-flow heat-exchange mode. An interposer cavity can be achieved by back-to-back bonding of interposer shells to achieve large channel heights. Sealing-ring structures and embedded TSVs are required to prevent contact between water and the electrically active TSVs. Optimal micro-channel dimensions of 150 μm width and 250 μm height were computed using an analytical convection model that considered mass and heat transfer. The impact of thermal interfaces arising from the electrical interconnects between the chip stack and the interposer was studied by numerical heat-conduction modeling. Neither, the interconnect type, rail or pillar, nor the application of thermally conductive underfills did result in significant changes in junction temperature. However, the dual-side cooling approach resulted in twice lower thermal gradients at the inlet of the cavity than with the back-side or front-side cooling option only. Although the cross-flow mode of the interposer increases the coolant temperature more than the cold plate, dual-side cooling extends the power dissipation limit for single dies and chip stacks substantially, supporting performance and efficiency scaling.

Thermal performance of a silicon-interposer with embedded fluid channels enabling dual-side heat removal

Future high-power chip stacks with several hundred Watts of power dissipation rely on novel cooling topologies. In this paper, we are introducing dual-side convective cooling considering a lid-integral silicon cold plate in combination with an interposer with embedded fluid cavity. The cavity in the interposer is established by two back-to-back bonded interposer shells with integrated fluid channels. This approach allows the implementation of a cavity height of 240 μm at a through-silicon-via pitch of 225 μm. Interposer test vehicles are fabricated to explore the heat removal capability of three different cavity designs; Channel 2-Port, Pin-Fin 2-Port and Channel 4-Port. They are studied with respect to their thermal response on uniform and non-uniform power maps. The projected power map of a three-tier chip stack with an aggregate power dissipation of more than 600W on 4cm2 area is considered. Heat and mass transport experiments are performed. Changes from laminar to transitional flow regimes are discussed. The transition is most prominent for the pin-fin cavity, indicated by a drastic pressure drop increase above 0.15 L/min and a junction temperature drop. The 4-port design with microchannels outperformed the other designs, considering pressure drop as the relevant boundary condition. The performance difference can be large especially for non-uniform heat fluxes and needs to be studied on a case-by-case basis.