P. Chakraborty

DIBL in short-channel strained-Si n-MOSFET

Drain-induced barrier lowering in substrate-induced strained-Si n-MOSFETs has been investigated. The variation of subthreshold swing as a function of both the gate length and gate to source voltage has also been examined.

Hot carrier degradation in nanowire (NW) FinFETs

Hot carrier reliability of a nanowire Omega-FinFET is investigated for the first time. Hot holes injected into the gate oxide via hot-carrier injection (HCI) at the silicon (Si) - silicon dioxide (SiO2) interface of Omega-FinFETs results in the formation of dangling silicon bonds due to the breaking of silicon-hydrogen bonds and lead to high interface traps generation. The trapping and/or bond breaking creates oxide charge and interface traps affect the Coulomb mobility. A quasi-two dimensional (quasi-2D) physics-based screening Coulomb scattering mobility model has been developed and implemented in Synopsys Sentaurus Device simulator.

Stress-induced degradation in strain-engineered nMOSFETs

Effects of electrical stress on DC performance of strain-engineered nMOSFETs are investigated using simulation. The applicability of technology CAD (TCAD) for the prediction of MOSFET reliability is demonstrated.

Scaling of Strain-Engineered MOSFETs

The aim of the present work is to study the evolution of Si based heterostructure MOSFETs via the incorporation of new materials, for example strained-Si, and to predict the resultant device performance and scaling trends of strained-Si/SiGe MOSFETs for RF applications. The article describes a comprehensive technology CAD (TCAD) based methodology to design and optimize strained-Si channel of CMOS technology using Sentaurus tools. Sentaurus-PROCESS is used to simulate and optimize a typical 90/45-nm process flow, including channel, halo, source/drain (S/D) profile engineering, oxidation, deposition, etching, and annealing for dopant activation. The structure generated by Sentaurus-PROCESS is then simulated using the device simulator Sentaurus-DEVICE. The simulation results have been benchmarked with reported experimental strained-Si channel MOSFET device results. The calibrated n- and p-type devices are scaled down to a 45 nm gate length to assess the device and circuit behavior.

Technology CAD of non-volatile SONOS memory devices

Scaled 100-nm gate length SONOS memory devices with a nitride layer embedded in the gate stack is studied using Technology CAD (TCAD). The program and erase states of the device are simulated. Long-term (10-year) charge retention capabilities of the SONOS structure are predicted.

RF performance of process-induced strain-engineered n-MOSFETs

Results of high frequency performance studies using technology CAD (TCAD) of process-induced strain- engineered n-MOSFETs with channel lengths down to 40 nm is reported. Uniaxial tensile stress induced in the channel using stressed contact liners were found to significantly improve ac performance, predicting a maximum oscillation frequency, fmax as high as 450 GHz. A record high cutoff frequency, fT of 380 GHz has been obtained in simulation, which, however, needs to be verified experimentally.

Radiation effects on strain-engineered p-MOSFETs

Effects of heavy ion irradiation on process- induced strained-Si (PSS) p-MOSFETs are studied via simulation. It is shown that for the immediate (short term), irradiation can cause degradation in the transconductance and drain current.

Reliability predictions for strained-Si/SiGe Quantum-well p-MOSFETs

Device simulation has been used to study the performance enhancement prediction for buried SiGe-channel p-MOSFETs. Steady state self-heating is modeled via the inclusion of thermal-flow analog auxiliary sub-circuits.