P. Chochula

Radiation tolerance of single-sided silicon microstrips

Abstract The RD20 collaboration is investigating the design and operation of an LHC inner tracking detector based on silicon microstrips. Measurements have been made on prototype detectors after irradiation with electrons, neutrons, photons, and protons for doses up to 5 Mrad and fluences up to 10 15 particles/cm 2 . The annealing of effective doping changes caused by high neutron fluences, one of the major limits to detector lifetime at the LHC, is shown to be strongly inhibited by cooling below room temperature. Detailed results are presented on the critical issue of microstrip capacitance. We have also investigated bulk damage caused by high-energy protons, interstrip isolation after neutron irradiation, and MOS capacitors irradiated with electrons and photons.

First results from the ALICE silicon pixel detector prototype

Abstract System prototyping of the ALICE silicon pixel detector (SPD) is well underway. The ALICE SPD consists of two barrel layers with 9.83 million channels in total. These are read out by the ALICE1LHCb pixel chip, which has been developed in a commercial 0.25 μm process with radiation hardening by design layout. The readout chip contains 8192 pixel cells each with a fast analog preamplifier and shaper followed by a discriminator and digital delay lines. Test results show a pixel cell noise of about 110 electrons rms and a mean minimum threshold of about 1000 electrons rms before threshold fine tuning. Several readout chips have been flip-chip bonded to detectors using two different bump-bonding techniques (solder, indium). Results of radioactive source measurements of these assemblies are presented for 90 Sr and 55 Fe sources. Several chip-detector assemblies have been tested in a 150 GeV / c pion beam at CERN where an online efficiency of about 99% across a wide range of detector bias and threshold settings was observed. All preliminary investigations confirm the functionality of the chip and the chip-detector assemblies for the ALICE experiment.

The Alice silicon pixel detector

CERN European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland Universita degli Studi di Padova, I-35131, Padova, Italy Dipartimento IA di Fisica e Sez. INFN di Bari, I-70126,Bari,Italy Comenius University, SK-84215 Bratislava, Slovakia NIKHEF, National Institute for Nuclear Physics and High Energy Physics, 1098 SJ Amsterdam, The Netherlands Slovak Academy of Sciences, SK-04353, Kosice, Slovakia Universita di Roma I, La Sapienza, I-00185, Roma, Italy

The DELPHI very forward tracker for LEP200

Abstract The design of a new silicon tracker detector for the forward region in the DELPHI experiment is presented. It consists of two layers of macropixel and two layers of ministrip detectors in both the forward directions. The motivations and the requirements for this detector will be shown together with test beam results.

The ALICE on-Detector pixel PILOT system-OPS

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) consists of 1,200 readout chips, bump-bonded to silicon sensors and mounted on the front-end bus, and of 120 control (PILOT) chips, mounted on a multi chip module (MCM) together with opto-electronic transceivers. The environment of the pixel detector is such that radiation tolerant components are required. The front-end chips are all ASICs designed in a commercial 0.25-micron CMOS technology using radiation hardening layout techniques. An 800 Mbit/s Glink-compatible serializer and laser diode driver, also designed in the same 0.25 micron process, is used to transmit data over an optical fibre to the control room where the actual data processing and event building are performed. We describe the system and report on the status of the PILOT system.

Irradiation and SPS Beam Tests of the Alice1LHCb Pixel Chip

The Alice1LHCb front-end chip [1,2] has been designed for the ALICE pixel and the LHCb RICH detectors. It is fabricated in a commercial 0.25 μm CMOS technology, with special design techniques to obtain radiation tolerance. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets (SEU), and with X-rays to evaluate the sensitivity to total ionising dose. We report the results of those measurements. We also report preliminary results of measurements done with 150 GeV pions at the CERN SPS.

The ALICE Pixel Detector Readout Chip Test System

The ALICE experiment will require some 1200 Readout Chips for the construction of the Silicon Pixel Detector [1] and it has been estimated that approximately 3000 units will require testing. This paper describes the system that was developed for this task.

The silicon pixel detector (SPD) for the ALICE experiment

The ALICE silicon pixel detector (SPD) constitutes the two innermost layers of the inner tracking system (ITS). The basic building block of the SPD is the half-stave carrying two detector ladders. The half-stave is equipped with a multi-chip module (MCM) and an optical fibre link for control and readout. A 5-layer aluminium/polyimide bus ensures the distribution of power and signals on each half-stave. The half-staves are mounted on a light-weight carbon-fibre structure with an integrated evaporative cooling system. An overview of the SPD development and the current status of the construction are presented.

Control and Monitoring of Front-End Electronics in ALICE

II. ARCHITECTURE OF ALICE ONLINE SYSTEMS Abstract Four systems are responsible for online operation of the ALICE sub-detectors: the Data Acquisition (DAQ), Trigger (TRG), High Level Trigger (HLT) and Detector Controls (DCS). Each system is partitioned following the ALICE detector architecture allowing for independent operation of individual sub-detectors and associated services. This paper describes the configuration and monitoring scheme, which is being developed for the ALICE Front-End Electronics (FEE). The scheme is common to all ALICE sub-detectors although each sub-detector has a different FEE architecture. It is based on a Front-End Device (FED) model, which removes the differences between the various systems and enables a common control approach to be applied. An implementation of the FED for the ALICE Silicon Pixel Detector is described. DCS for each sub-detector is segmented into sub-systems. It treats the high voltage (HV), low voltage (LV), cooling, gas control and FEE individually. DCS coordinates operation of its sub-systems.

The ALICE detector control system

ALICE is one of the six currently installed experiments at the Large Hadron Collider (LHC) at CERN (Geneva, Switzerland). The experiment saw its first particles during the commissioning of the LHC accelerator in 2008 and is now preparing for the first physics runs foreseen for the autumn of 2009. The experiment is composed of a large number of sub-detectors, each with up to 15 different subsystems that need to be controlled and operated in an efficient and reliable way. For this purpose, a Detector Control System (DCS) has been developed based on latest technologies and using new and innovative approaches. The DCS system has been used with success during the commissioning of the individual detectors as well as during the cosmic runs and the LHC injection tests that were carried out in 2008. This paper gives an overview of the control system and it describes the architecture, the tools and the components that have been used to build it. Examples of technical implementations are given and new trends and techniques used in the system are highlighted.