P.D. Fisher

A scan design for asynchronous sequential logic circuits using SR-latches

This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.<<ETX>>

ASLCScan: A scan design technique for asynchronous sequential logic circuits

Asynchronous sequential logic circuits (ASLCs) are synthesized with either the Huffman model, referred to as HMASLCs, or with the signal transition graph (STG), referred to as STGASLCs. Based on a single stuck-at fault model, this paper describes fault effects for both HMASLCs and STGASLCs and addresses the similarities and differences between them. The fault effects include redundant faults and state oscillations. Input/output redundancy is a special feature of STGASLCs which relaxes the fundamental mode in HMASLCs. Results of this study show that the faults due to the input/output concurrency cannot be tested without a scan structure. This paper presents a scan design technique. ASLCScan. With this structure, the test generation problem is reduced to one of just testing the combinational logic.<<ETX>>

An efficient modeling and synthesis procedure of asynchronous sequential logic circuits

A model and procedure are developed for synthesizing asynchronous sequential logic circuits (ASLCs). This model represents the functional behavior with a more compact form and the procedure can synthesize them more efficiently than the traditional one. With the identification of edge inputs from the design specification, a set of equations can be generated which describes the functional behavior of the logic module. The calculated states from these equations can easily be mapped onto an n-cube to obtain a race-free assignment. Further delineation of mode inputs and level inputs from data inputs facilitates the process of decomposing complex logic functions into smaller ones which can be more easily synthesized.<<ETX>>

An artificial intelligence approach to the behavioral modeling of asynchronous sequential logic circuits

A method has been developed which uses artificial intelligence techniques to model the functional behaviour of asynchronous sequential logic circuits (ASLCs). It provides a highly structured, interactive approach. The domain representation, production rules, and control strategy are described. The behavioural descriptor of the ASLC design automation system generates a primitive flow table which captures the ASLCs functional behaviour. This methodology has been implemented in the C programming language and currently resides on Sun workstations. This ASLC design automation system has been validated using numerous representative examples and has been found to be much quicker and more reliable than more traditional methods for designing ASLCs.<<ETX>>

A synthesis procedure for large-scale asynchronous finite state machines

This paper presents an efficient synthesis procedure for asynchronous finite state machines (FSMs). A merged flow table is first generated from a behavioral description of a FSM. Based on the bipartite characteristics of the adjacency diagram, a race-free state assignment algorithm using bipartite graphs is applied. Several MCNC FSM benchmarks have been tested. Results show that the presented procedure can handle reasonably large asynchronous FSMs.<<ETX>>

An efficient two-layer irregular-channel router

An efficient two-layer irregular-channel router is presented which is suitable for both regular and irregular channels. The router uses a heuristic approach to determine all of the subnet-weights for a given channel. It constructs the maximum subnet-weight path in order to determine the best set of subnets for each track. For a given irregular channel, the obstacles are treated as subnets with a highest weight, which reduces the irregular channel-routing to a regular channel-routing. Also, user intervention is permitted by the router for generating a minimum wire length for the specified net. In addition, since this router uses restricted doglegging, the likelihood for it to process a cyclic routing channel is reduced. By using an intermediate routing format, the CF router can easily be used in conjunction with the CF mask generator to generate masks. The CFR router is shown to be very effective in generating acceptable results quickly for both regular and irregular channels.<<ETX>>

Application of bipartite graphs for achieving race-free state assignments

Achieving race-free state assignments is an important objective in the synthesis of asynchronous sequential logic circuits (ASLCs). Traditionally, adjacency diagrams are used to help identify and resolve race conditions; however, this approach has a high degree of computational complexity. This paper presents an efficient state assignment algorithm that utilizes a pattern matching technique to predict races and to eliminate the need for enumerative searches. More specifically, the race-free state assignment problem is formulated as the embedding of a bipartite connected graph onto an n-cube and achieves a near minimum number of state variables. This algorithm has been evaluated using several representative examples. Results show that the developed algorithm provides better performance than existing algorithms. Due to the simplicity of the bipartite representation of an n-cube, the developed algorithm is suitable for ASLC synthesis that may involve a relatively large number of states. >

Race-free state assignments using bipartite graphs

The authors present a race-free state assignment algorithm which maps a bipartite adjacency diagram (BAT) to an n-cube. With the bipartite representation table (BRT) for an n-cube, the problem of embedding of a BAT in an n-cube is equivalent to that of matching the patterns of the BAT and the BRT. Based on the special characteristics of the BAT, several matching rules are presented to solve the problem. Experimental results have shown that the algorithm is better than existing algorithms in terms of compute time, particularly for encoding states of large asynchronous sequential logic circuits.<<ETX>>

Model of asynchronous finite state machines and their pipelined structures

The design of asynchronous finite state machines (AFSMs) has been limited because multiple-input changes are disallowed. A new architecture for designing AFSMs with completion signals, in which the completion signal is generated whenever both outputs and internal states stabilize, is presented. Results show that the proposed design allows multiple-input changes and is free of races and hazards. Based on the proposed architecture, a pipelined AFSM structure is presented.<<ETX>>