P. Giannetti

The CDF Central and Endwall Hadron Calorimeter

Abstract The CDF central and endwall hadron calorimeter covers the polar region between 30° and 150° and a full 2π in azimuth. It consists of 48 steel-scintillator central modules with 2.5 cm sampling and 48 steel-scintillator endwall modules with 5.0 cm sampling. A general description of the detector is given. Calibration techniques and performance are discussed. Some results of the test beam studies are shown.

Associative memory design for the fast track processor (FTK) at ATLAS

We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.

The SVT Hit Buffer

The Hit Buffer is part of the Silicon Vertex Tracker [1], a trigger processor dedicated to the reconstruction of particle trajectories in the Silicon Vertex Detector [2] and the Central Tracking Chamber of the Collider Detector at Fermilab. The Hit Buffer is a high speed data-traffic node, where thousands of words are received in arbitrary order and simultaneously organised in an internal structured data base, to be later promptly retrieved and delivered in response to specific requests. The Hit Buffer is capable to process data at a rate of 25 MHz, thanks to the use of special fast devices like Cache-Tag RAMs and high performance Erasable Programmable Logic Devices from the XILINX XC7300 family.

Fastbus data acquisition for CDF

Abstract All CDF event data are collected in a multilevel FASTBUS network. At the lowest level of this network, MEP/MX and SSP scanners read and buffer data from RABBIT and FASTBUS front end systems. Operation of these front end scanners is coordinated by the Trigger Supervisor module which initiates parallel readout after receiving Level 1 and Level 2 triggers. Dataflow from scanners to consumer processes on host VAX computers is supervised by the Buffer Manager which directs an Event Builder to collect and format data from a set of scanner modules. This system is designed to allow partitioning into semi-independent sections for parallel development and calibration studies.

The fast tracker processor for hadron collider triggers RID C-4866-2008

Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times.

The CDF online silicon vertex tracker

The CDF Online Silicon Vertex Tracker (SVT) reconstructs 2D tracks by linking hit positions measured by the Silicon Vertex Detector to the Central Outer Chamber tracks found by the eXtremely Fast Tracker (XFT). The system has been completely built and assembled and it is now being commissioned using the first CDF run II data. The precision measurement of the track impact parameter will allow triggering on B hadron decay vertices and thus investigating important areas in the B sector, like CP violation and B(s) mixing. In this paper we briefly review the architecture and the tracking algorithms implemented in the SVT and we report on the performance of the system achieved in the early phase of CDF run II.

Level-2 calorimeter Trigger Upgrade at CDF

The CDF Run II Level-2 calorimeter trigger is implemented in hardware and is based on an algorithm used in Run I. This system insured good performance at low luminosity obtained during the Tevatron Run II. However, as the Tevatron instantaneous luminosity increases, the limitations of the current system due to the algorithm start to become clear. In this paper, we will present an upgrade of the Level-2 calorimeter trigger system at CDF. The upgrade is based on the Pulsar board, a general purpose VME board developed at CDF and used for upgrading both the Level-2 tracking and the Level-2 global decision crate. This paper will describe the design, hardware and software implementation, as well as the advantages of this approach over the existing system.

A pipeline of associative memory boards for track finding RID C-4866-2008

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next Large Hadron Collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with a low-cost commercial field-programmable gate array (FPGA). FPGA programming has been optimized for maximum efficiency in terms of pattern density, while printed circuitboard design has been optimized in terms of modularity and FPGA chip density. A complete associative memory board has been successfully tested at 40 MHz; it can contain 7.2/spl times/10/sup 3/ particle trajectories.

Position sensitive silicon detectors inside the tevatron collider

Abstract Four position sensitive silicon detectors have been tested inside the Tevatron beam pipe at Fermilab. The system is the prototype of the small angle silicon spectrometer designed to study primarily p p elastic and diffractive cross-sections at the Collider of Fermilab (CDF). Particles in the beam halo during p - p storage tests were used to study the performance of the detectors. Efficiency, linearity of response and spatial resolution are shown. Measurements performed at different distances from the beam axis have shown that the detectors could be operated at 8.5 mm from the beam with low rates and no disturbance to the circulating beams. This distance corresponds to about 11 times the standard half-width of the local beam envelope. The behaviour of the detectors with the radiation dose has also been investigated.

Level-3 calorimeter resolution available for the Level-1 and Level-2 CDF triggers

As the Tevatron luminosity increases more sophisticated selections are required to be efficient in selecting rare events from a very huge background. To cope with this problem, CDF has pushed the Level-3 calorimeter algorithm resolutions up to Level-2 and, when possible, at Level-1, increasing efficiency and, at the same time, keeping under control the rates. This strategy increases the purity of the Level-2 and Level-1 samples, produces free-bandwidth that allows to reduce the thresholds. The global effect is an increase of the signal efficiency of important Tevatron Standard Model Higgs search channels (H → WW, ZH, WH). The L2 upgrade improves the cluster finding algorithm, the resolution of the Missing Transverse Energy (MET) and the SUM Transverse Energy (SUMET) calculations. The same Level-2 MET and SUMET improved resolution has been made available to the Level-1 system, exploiting the same hardware used for the Level-2 upgrade. The upgrade is based on the Pulsar board, a general purpose VME board developed at CDF and already used for upgrading both the Level-2 tracking and the Level-2 global decision crate. The Level-2 upgrade has been designed, built, tested and commissioned in six months. It was accepted as the default system for CDF in August 2007. The same Level-2 hardware can be used in such a way to provide the Level-1 calorimeter system of the same MET, SUMET resolution provided to Level-2. While in the upgraded Level-2 system the algorithms are executed in a commercial CPU within the typical Level-2 processing timing of 20 μs, in the upgraded Level-1 system, MET and SUMET are calculated by powerful FPGAs within 5 μs. The Level-1 upgrade is currently ongoing and in commissioning phase.We describe the CDF Level-2 and the new Level-1 calorimeter upgrades, the architecture and the trigger performances, with particular emphasis on a new calorimeter MET_JET-based trigger performances used for CDF Higgs search.