P. Kind

The power supply system for the ATLAS pixel detector

The innermost part of the ATLAS (A Toroidal LHC Apparatus) experiment at the LHC (Large Hadron Collider), CERN (Conseil Eurpeenne pour la Recherche Nucleaire), will be a pixel detector, which is presently under construction. To operate the approx. 1700 detector modules and their related readout electronics a sophisticated power supply system is required. Its design constraints are the high power density and the sensitivity of the read out chips developed in deep sub-micron technology. A high granularity of the system is desired to allow individual adjustment and to minimize the number of elements out of service. We describe the layout of the full power supply system and concentrate on the components designed in-house: the supply system for the optical link, which offers the possibility of handling a high number of channels at a reasonable price and the remotely-programmable regulator stations, which protect the sensitive front end electronics.

The hardware of the ATLAS Pixel Detector Control System

The innermost part of the ATLAS (A Toroidal LHC ApparatuS) experiment, which is currently under construction at the LHC (Large Hadron Collider), will be a silicon pixel detector comprised of 1744 individual detector modules. To operate these modules, the readout electronics, and other detector components, a complex power supply and control system is necessary. The specific powering and control requirements, as well as the custom made components of our power supply and control systems, are described. These include remotely programmable regulator stations, the power supply system for the optical transceivers, several monitoring units, and the Interlock System. In total, this comprises the Pixel Detector Control System (DCS).

Studies for the detector control system of the ATLAS pixel at the HL-LHC

In the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be a new pixel de- tector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

The control system for the ATLAS pixel detector

A pixel detector is under construction for A Toroidal LHC ApparatuS (ATLAS) experiment, which will utilize the large hadron collider (LHC) at Conseil Europe/spl acute/enne pour la Recherche Nucle/spl acute/aire (CERN). Due to the large number of channels, a data-intensive control system will be required. The choice and design of the requisite hardware for this control system is mainly driven by a high power density and a harsh radiation environment. This includes the development of an interlock system to ensure the safety of the detector, and a special control and supply system for the operation of the optical link connection to the data acquisition (DAQ) readout chain. Given the complexity of the required assembly, a commercial supervisory control and data acquisition (SCADA) system is used. Based on this, we have developed a geographical approach, which matches the different hardware components for the operation of one detector part to uniform software elements. Its tree structure allows clear control of a large amount of information. For the final design, where several SCADA systems are linked, a distributed system is necessary. We have shown this system to work efficiently and will discuss first experiences.

System Tests of the ATLAS Pixel Detector

The innermost part of the ATLAS (A Toroidal LHC ApparatuS)[1] experiment at the LHC (Large Hadron Collider) will be a pixel detector, which is presently under construction. Once installed into the experimental area, access will be extremely limited. To ensure that the integrated detector assembly operates as expected, a fraction of the detector which includes the power supplies and monitoring system, the optical readout, and the pixel modules themselves, has been assembled and operated in a laboratory setting for what we refer to as system tests. Results from these tests are presented.

Prototype Chip for a Control System in a Serial Powered Pixel Detector at the ATLAS Phase II Upgrade

A new inner tracking detector for the Phase-II upgrade of the ATLAS experiment is in development. A serial power scheme is foreseen for the pixel detector. This requires a new detector control system to monitor and control the pixel modules in the serial power chain. The Pixel Serial Power Protection (PSPP) chip is an ASIC for this purpose. It operates parallel to the modules and contains an ADC and bypass transistor. This paper presents test results for the prototyped PSPP chip. It includes irradiation up to 600 Mrad and longterm measurements. The third version of the PSPP chip is functional and will be used for tests with serial power chains together with pixel modules.

Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerators luminosity by a factor of 10. In the context of this upgrade, the inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

Radiationhard components for the control system of a future ATLAS pixel detector

The upgrade of the ATLAS experiment for the High Luminosity LHC (HL-LHC) will include a new pixel detector. A completely new detector control system (DCS) for this pixel detector will be required in order to cope with the substantial increase in radiation at the HL-LHC. The DCS has to have a very high reliability and all components installed within the detector volume have to be radiationhard. This will ensure a safe operation of the pixel detector and the experiment. A further design constraint is the minimization of the used material and cables in order to limit the impact on the tracking performance to a minimum. To meet these requirements we propose a DCS network which consists of a DCS chip and a DCS controller. In the following we present the development of the first prototypes for the DCS chip and the DCS controller with a special focus on the communication interface, radiation hardness and robustness against single event upsets.