P. Pangaud

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described followed by the simulation and measurement results.

HV/HR-CMOS sensors for the ATLAS upgrade-concepts and test chip results

In order to extend its discovery potential, the Large Hadron Collider (LHC) will have a major upgrade (Phase II Upgrade) scheduled for 2022. The LHC after the upgrade, called High-Luminosity LHC (HL-LHC), will operate at a nominal leveled instantaneous luminosity of 5× 1034 cm−2 s−1, more than twice the expected Phase I . The new Inner Tracker needs to cope with this extremely high luminosity. Therefore it requires higher granularity, reduced material budget and increased radiation hardness of all components. A new pixel detector based on High Voltage CMOS (HVCMOS) technology targeting the upgraded ATLAS pixel detector is under study. The main advantages of the HVCMOS technology are its potential for low material budget, use of possible cheaper interconnection technologies, reduced pixel size and lower cost with respect to traditional hybrid pixel detector. Several first prototypes were produced and characterized within ATLAS upgrade R&D effort, to explore the performance and radiation hardness of this technology. In this paper, an overview of the HVCMOS sensor concepts is given. Laboratory tests and irradiation tests of two technologies, HVCMOS AMS and HVCMOS GF, are also given.

Characterization of fully depleted CMOS active pixel sensors on high resistivity substrates for use in a high radiation environment

Depleted CMOS active sensors (DMAPS) are being developed for high-energy particle physics experiments in high radiation environments, such as in the ATLAS High Luminosity Large Hadron Collider (HL-LHC). Since charge collection by drift is mandatory for harsh radiation environment, the application of high bias voltage to high resistive sensor material is needed. In this work, a prototype of a DMAPS was fabricated in a 150nm CMOS process on a substrate with a resistivity of >2 kΩ·cm that was thinned to 100 μm. Full depletion occurs around 20V, which is far below the breakdown voltage of 110 V. A readout chip has been attached for fast triggered readout. Presented prototype also uses a concept of sub-pixel en/decoding three pixels of the prototype chip are readout by one pixel of the readout chip. Since radiation tolerance is one of the largest concerns in DMAPS, the CCPD_LF chip has been irradiated with X-rays and neutrons up to a total ionization dose of 50 Mrad and a fluence of 1015neq/cm2, respectively.

Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.

PIXSIC: A Pixellated Beta-Microprobe for Kinetic Measurements of Radiotracers on Awake and Freely Moving Small Animals

We present a design study of PIXSIC, a new β+ radiosensitive microprobe implantable in rodent brain dedicated to in vivo and autonomous measurements of local time activity curves of beta radiotracers in a small (a few mm3) volume of brain tissue. This project follows the initial β microprobe previously developed at IMNC, which has been validated in several neurobiological experiments. This first prototype has been extensively used on anesthetized animals, but presents some critical limits for utilization on awake and freely moving animals. Consequently, we propose to develop a wireless setup that can be worn by an animal without constraints upon its movements. To that aim, we have chosen a Silicon-based detector, highly β sensitive, which allows for the development of a compact pixellated probe (typically 600 × 200 × 1000 μm3), read out with miniaturized wireless electronics. Using Monte-Carlo simulations, we show that high resistive Silicon pixels are appropriate for this purpose, assuming that the pixel dimensions are adapted to our specific signals. More precisely, a tradeoff has to be found between the sensitivity to β+ particles and to the 511 keV j background resulting from annihilations of β+ with electrons. We demonstrate that pixels with maximized surface and minimized thickness can lead to an optimization of their β+ sensitivity with a relative transparency to the annihilation background.

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown.

Simulations of depleted CMOS sensors for high-radiation environments

After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

Simulation Results for PLATO: A Prototype Hybrid X-Ray Photon Counting Detector with a Low Energy Threshold for Fusion Plasma Diagnostics

PLATO is a prototype hybrid X-ray photon counting detector that has been designed to meet the specifications for nplasma diagnostics for the WEST tokamak platform (Tungsten (W) Environment in Steady-state Tokamak) in southern nFrance, with potential perspectives for ITER. The objective is to detect X-ray fluorescence photons emitted by a ntokamak plasma at energies as low as 3 keV. Therefore, PLATO represents a customized solution that fulfills high nsensitivity, low dispersion and high photon counting rate. The PLATO prototype matrix is composed of 16 x 16 pixels nwith a 70 μm pixel pitch. Each pixel contains a charge sensitive amplifier, two discriminators and two 12-bit counters/ nshift registers. New techniques have been used in analog sensitive blocks to minimize noise coupling through supply nrails and substrate, and to suppress threshold dispersion across the matrix. For an input capacitance of 250 fF and a nmaximum photon counting rate of 12 × 107 photons/s/mm2, simulation results indicate an input referred equivalent nnoise charge of 42 e-rms and a high response linearity for photon energies between 2 and 10 keV. A new feedback ntechnique has been implemented that allows a very high conversion gain of 72 mV/ke- while maintaining low pixel to npixel dispersion. Moreover, the pixel has been optimized for low power consumption of 5.2 μW/pixel. The pixel can be nprogrammed in a ‘two energy threshold’ mode with 2 x 12-bit counters, or ‘one energy threshold’ mode with a 24-bit ncounter. Furthermore, leakage current is compensated up to 10 nA/pixel. The Plato ASIC has been designed in TSMC nCMOS 0.13 μm technology and is scheduled for a fabrication run in May 2016. The prototype chip should be tested nelectrically, as well as bump bonded to silicon detector

IMIC — needle-shaped low-power monolithic active pixel sensor for molecular neuroimaging on awake and freely moving rats

IMIC is a Monolithic Active Pixel Sensor prototype for the MAPSSIC project dedicated to direct detection of low energy β+ rays in the brain of awake and freely-moving rats using CMOS technology. Former experiments using a β+ Si probe developed within the PIXSIC project validated a methodological proof of concept. However, conducting routinely such measurements would require improvements with respect to the passive pixel sensors employed in PIXSIC. The new IMIC circuit is fabricated in a 180 nm CMOS Image Sensor Technology and features a matrix of 16 × 128 pixels, which are 30 × 50 μm2 large. The sensor has a needle-like aspect ratio (610 μm × 12 000 μm). The chip is produced on a 18 μm high-resistivity epitaxial layer substrate. The foreseen application requires high sensitivity to β-rays while being immune to background γ-rays. Another severe constraint is the limited power dissipation in order to minimize the thermal impact on the brain. IMIC is a fully-programmable digital sensor. The pixel design is based on the front-end architecture of the ALPIDE chip. However modifications have been made to store the information inside fired pixels between two readouts allowing low data throughput. The circuit is controlled through the SPI protocol, which allows for setting all the necessary polarization signals. The results of post-layout simulations show a high signal to noise ratio (>40) and low power dissipation of 115 μW/matrix. Laboratory characterization using β-rays validate these predictions and demonstrated that the slow readout can cope with the expected low activity (≍ 120 hits/matrix/s).

Test results of the first 3D-IC prototype chip developed in the framework of HL-LHC/ATLAS hybrid pixel upgrade

To face new challenges brought by the upgrades of the Large Hadron Collider at CERN and of ATLAS pixels detector, for which high spatial resolution, very good signal to noise ratio and high radiation hardness are needed, 3D Integrated Technologies are investigated. Commercial offers of such technologies are only very few and the 3D designers choice is as a consequence strongly constrained. We present here the test results of the first 3D prototype chip developed in the GlobalFoundries 130 nm chips processed by the Tezzaron Company, submitted within the 3D-IC consortium for which a reliable qualification program was developed. Reliability and influence on the integrated devices behavior of Bond Interface (BI) and Through Silicon Via (TSV) connections, both needed for the 3D integration process, has also been addressed by the tests.