S. Godiot

Hardware Architecture and Cutting-Edge Assembly Process of a Tiny Curved Compound Eye

The demand for bendable sensors increases constantly in the challenging field of soft and micro-scale robotics. We present here, in more detail, the flexible, functional, insect-inspired curved artificial compound eye (CurvACE) that was previously introduced in the Proceedings of the National Academy of Sciences (PNAS, 2013). This cylindrically-bent sensor with a large panoramic field-of-view of 180° × 60° composed of 630 artificial ommatidia weighs only 1.75 g, is extremely compact and power-lean (0.9 W), while it achieves unique visual motion sensing performance (1950 frames per second) in a five-decade range of illuminance. In particular, this paper details the innovative Very Large Scale Integration (VLSI) sensing layout, the accurate assembly fabrication process, the innovative, new fast read-out interface, as well as the auto-adaptive dynamic response of the CurvACE sensor. Starting from photodetectors and microoptics on wafer substrates and flexible printed circuit board, the complete assembly of CurvACE was performed in a planar configuration, ensuring high alignment accuracy and compatibility with state-of-the art assembling processes. The characteristics of the photodetector of one artificial ommatidium have been assessed in terms of their dynamic response to light steps. We also characterized the local auto-adaptability of CurvACE photodetectors in response to large illuminance changes: this feature will certainly be of great interest for future applications in real indoor and outdoor environments.

Performance and Applications of the CdTe- and Si-XPAD3 photon counting 2D detector

The XPAD3 is the third generation of a single photon counting chip developed in collaboration by SOLEIL Synchrotron, the Institut Neel and the Centre de Physique de Particules de Marseille (CPPM). The chip contains 9600 pixels of 130 μm side and a counting electronic chain with an adjustable low level threshold in each pixel. Imaging and detection performance (detective quantum efficiency, modulation transfer function and energy resolution) of the XPAD3 detectors hybridized with Si and CdTe sensors have been evaluated and compared using monochromatic synchrotron X-rays beam. A second version of the chip, optimized for pump-probe experiments, has been realized and successfully tested. Three 7.3 cm x 12.5 cm Si-XPAD3 imagers, composed of 8 silicon modules (7 chips per module) and one 2.1 cm x 3.1 cm CdTe-XPAD3 imager (4 chips) have been constructed and successfully used for synchrotron diffraction experiments and biomedical imaging.

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described followed by the simulation and measurement results.

Characterization of fully depleted CMOS active pixel sensors on high resistivity substrates for use in a high radiation environment

Depleted CMOS active sensors (DMAPS) are being developed for high-energy particle physics experiments in high radiation environments, such as in the ATLAS High Luminosity Large Hadron Collider (HL-LHC). Since charge collection by drift is mandatory for harsh radiation environment, the application of high bias voltage to high resistive sensor material is needed. In this work, a prototype of a DMAPS was fabricated in a 150nm CMOS process on a substrate with a resistivity of >2 kΩ·cm that was thinned to 100 μm. Full depletion occurs around 20V, which is far below the breakdown voltage of 110 V. A readout chip has been attached for fast triggered readout. Presented prototype also uses a concept of sub-pixel en/decoding three pixels of the prototype chip are readout by one pixel of the readout chip. Since radiation tolerance is one of the largest concerns in DMAPS, the CCPD_LF chip has been irradiated with X-rays and neutrons up to a total ionization dose of 50 Mrad and a fluence of 1015neq/cm2, respectively.

Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.

Test results and irradiation performances of 3-D circuits developed in the framework of ATLAS hybrid pixel upgrade

Vertex detectors for High Energy Physics experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3-D designers choice is then hardly constrained. Moreover, as radiation hardness and specially SEU tolerance of configuration registers is a crucial issue for SLHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the design and test (including radiation tests with 70 kV, 60W X-Ray source and 24 GeV protons) of Chartered, 130nm Low Power 2-D chips realized for this qualification.

Upgrades of the HL-LHC/ATLAS hybrid pixels detector: Test results of the first 3D-IC prototype

Vertex detectors for High Energy Physic experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of the upgrades of HL-LHC/ATLAS future hybrid pixel vertex detectors is to use the emerging 3D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3D designers choice is then very much constrained. Moreover, as radiation hardness and in particular SEU tolerance of configuration registers is a crucial issue for HL-LHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the test results of GlobalFoundries, 130 nm chips processed by Tezzaron Company, submitted within the 3D-IC consortium. Reliability and influence of these 3D connections on integrated devices behavior has also been addressed by tests.

CURVACE - CURVed Artificial Compound Eyes

CURVACE aims at designing, developing, and assessing CURVed Artificial Compound Eyes, a radically novel family of vision systems. This innovative approach will provide more efficient visual abilities for embedded applications that require motion analysis in low-power and small packages. Compared to conventional cameras, artificial compound eyes will offer a much larger field of view with negligible distortion and exceptionally high temporal resolution in smaller size and weight that will fit the requirements of a wide range of applications.

A Tezzaron-Chartered 3D-IC electronic for SLHC/ATLAS hybrid pixels detectors test results and irradiations performance

The ATLAS pixel collaboration has started in 2008 a R&D program to use the latest advances in 3-D electronics technology in order to develop a new Front-End (FE) chip for a vertex detector for High Energy Physics (HEP). This program using the commercial Tezzaron-Chartered 0.13µm LP technology should be able to fulfill the requirements imposed by the ten times higher luminosity given by the High Luminosity LHC accelerator. The FE-TC4-P1 is a hybrid pixel read-out chip realized by the first MPW for HEP. This three dimensional chip includes an analog part called FE-TC4-AE and two digital parts called FE-TC4-DS and FE-TC4-DC. At the same time, several prototypes were realized in Chartered 0.13µm LP technology, in order to disentangle from effects induced by 3D architecture. These FE-C4-P1,2,3 prototypes have proved a good radiation hardness up to 400Mrads as well as good performances. This paper presents results from the FE-TC4-P1 chip which has been recently tested and irradiated.

Development of a PCI express based readout electronics for the XPAD3 X-ray photon counting imager

XPAD3 is a large surface X-ray photon counting imager with high count rates, large counter dynamics and very fast data readout. Data are readout in parallel by a PCI Express interface using DMA transfer. The readout frame rate of the complete detector comprising 0.5 MPixels amounts to 500 images per second without dead-time.