P. Petkovic

Fault location in passive analog RC circuits by measuring impulse response

In this paper modified impulse response estimation method is described. After recalling the general problems of automatic symbolic function generation, and a basis of impulse response estimation method, expanding of this method is proposed. This paper deals with fault location of single fault in analog electronic circuits. In the paper, an example of this approach is given. Finally, the utility of this method when two faults occured in a circuit is considered.

A hierarchical approach to large circuit symbolic simulation

Abstract This paper presents a new approach to symbolic analysis of large circuits. The proposed procedure is grounded on circuit decomposition by node tearing, symbolic analysis at subcircuit level and circuit function generation. Symbolic analysis is based on matrix-determinant method implemented within our original symbolic simulator. The crucial part of this procedure is circuit function generation. Opposed to classic symbolic simulation that gives final result in canonical sum-of-product form, hierarchical approach results in compact nested form. Proposed method is described in details using a simple example. The comparison with two other similar techniques is given using a benchmark example. The overall time reduction in comparison with the circuit function extraction in fully expanded form is 30 times.

ANN Application to Modelling of the D/A and A/D Interface for Mixed-mode Behavioural Simulation

Artificial neural networks are applied for modeling the input and output circuits of the digital part of the digital–analog and analog–digital interface, respectively, in CMOS mixed-mode circuits. The generalization property of the neural networks is exploited to apply the models in a set of previously unknown situations, the most important being loading the model generated from the unloaded circuit. The models developed are applicable in mixed-signal behavioral simulations.

Reordering in Topology Decision Diagram Method for Symbolic Circuit Analysis

This paper introduces reordering method in topology decision diagram (TDD) in order to enhance symbolic analysis method for RLC gm network function generation in nested form. The improvement is obtained in circuit function compression and the execution time. An example of n-th order ladder network illustrates the method

Symbolic fault modelling of MOS combinational circuits

This paper presents a new method for fault modelling of MOS combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate. Moreover, the method can deal also with bridging and cut faults. Finally, the application of the TLCF for test pattern generation is considered.

DETECTION OF POWER GRID HARMONIC POLLUTION SOURCES BASED ON UPGRADED POWER METERS

Abstract The paper suggests a new and efficient method for location of nonlinear loads on a grid. It is based on measuring of distortion power. The paper reviews different definitions of distortion power and proves that the method is feasible independently on particular definition. The obtained results of simulation and measurement confirm the effectiveness and applicability of the method. The proposed solution is suitable for software update of existing electronic power-meters or can be implement as hardware upgrade.

A second order s-to-z transform and its implementation to IIR filter design

Purpose – The purpose of this paper is to design a tool for IIR digital filters obtained from analog prototypes, which preserves simultaneously the amplitude and the group delay response. Design/methodology/approach – A new s-to-z transform is developed based on a second order formula used for numerical integration of differential equations. Stability of the newly obtained transfer functions in the z-domain is proved to be preserved. Distortions introduced by the new transform into the original amplitude and group delay responses are studied. Findings – The new formula, when implemented to all-pole prototypes, exhibits lower selectivity than the original while reducing the pass-band group delay distortions. In the same time its structure is importantly simpler than the functions obtained by the well-known bilinear transform. When implemented to a prototype having “all kinds” of transmission zeros the resulting filter has almost ideally the same characteristic as the prototype. Research limitations/implica...

Time domain black-box modelling of CMOS structures and analog timing simulation

A new macromodeling procedure for CMOS LSI circuits is proposed. Problems concerned with transient properties of the macromodel are explored and solved. The macroanalysis is performed at gate level, the level most frequently used for logic simulation. However, the accuracy of the model used for macroanalysis is still better so that these two types of network verification do not exclude each other. The problem of propagation-delay modeling is solved by implementation of an analog controlled voltage source, while the problem of output resistance modeling is solved by a resistor whose value is controlled by the output voltage.<<ETX>>

SMARTER POWER METERS REDUCE ECONOMIC LOSSES AT UTILITY

Whenever the delivered power is greater than the sum of the registered power at points of common coupling (PCC) the utility will have losses. This paper will show that even in an ideal case, without any abuse of users, the losses occur due to inadequate measurement equipment and to deficient billing policy. Namely, common household power meters register only active energy, while power meters for industrial applications register reactive energy as well. Consequently, the billing policy is based only at one or both values. This approach does not follow the change of the end-user load profile that becomes very nonlinear. Actually, the current trough nonlinear load deviates from sine waveform causing that a part of the delivered power remains invisible for the power distribution system. Therefore, the utility registers significant economic losses. To solve this problem we recommend distortion power to be measured and included into the billing policy. It has not been the case so far because the electric power community has not been aware of the amount of the distortion power in the contemporary grid. Besides, power meters have not been able to measure it. This paper demonstrates how to overcome the obstacle with a minor modification of ordinary electronic power meters. The proposed solution is verified by a set of measurements on different types of loads that are commonly used in households and offices.

Design for testability for SoC based on IDDQ scanning

One DFT solution for systems on chip, based on IDDQ measuring concept is presented in this paper. The application of Reconfigurable neurai networks off chip enables also good diagnostics capabilities. The solution is to be implemented in few digital blocks of the tree phase power meter IC and realized using CMOS035 technology. The simulation results obtained using Cadence Virtuoso show good performances of the solution.