D. Milovanovic

Fault location in passive analog RC circuits by measuring impulse response

In this paper modified impulse response estimation method is described. After recalling the general problems of automatic symbolic function generation, and a basis of impulse response estimation method, expanding of this method is proposed. This paper deals with fault location of single fault in analog electronic circuits. In the paper, an example of this approach is given. Finally, the utility of this method when two faults occured in a circuit is considered.

Fault models of CMOS circuits

Abstract A systematic procedure for fault modelling of CMOS circuits is described. It starts with the physical fault and produces a set of tables describing the logic behaviour of the gate. This set of tables is referred to as the fault model and includes truth tables, fault equivalence tables, fault coverage tables, and fault propagation tables. Starting with the procedure of fault modelling of simple combinational circuits, a method is advised for model generation of complex sequential structures. Application of fault modelling for yield evaluation and test pattern generation is considered, too.

Fault models of CMOS transmission gate

New CMOS transmission gate (TG) fault models are described. The TG is observed as a bilateral logic circuit. Its fault models are obtained using a mathematical circuit analysis of the elementary network and these are verified using the electronic circuit analysis rogram MOST. Another topic covered by the aper is faulty state ropagation through the TG. The results of the research described above enable successful fault simulation of circuits containing transmission gates

Symbolic fault modelling of MOS combinational circuits

This paper presents a new method for fault modelling of MOS combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate. Moreover, the method can deal also with bridging and cut faults. Finally, the application of the TLCF for test pattern generation is considered.

HIERARCHICAL APPROACH TO DIAGNOSIS OF MIXED-MODE CIRCUITS USING ARTIFICIAL NEURAL NETWORKS

Feed-forward artiflcial neural networks (ANNs) have been applied to the diagnosis of mixed-mode electronic circuit. In order to tackle the circuit com- plexity and to reduce the number of test points, hierarchical approach to the diag- nosis generation was implemented with two levels of decision: the system level and the circuit level. For every level, using the simulation-before-test (SBT) approach, fault dictionary was created flrst, containing data relating to the fault code and the circuit response for a given input signal. ANNs were used to model the fault dictio- naries. During the learning phase, the ANNs were considered as an approximation algorithm to capture the mapping enclosed within the fault dictionary. Later on, in the diagnostic phase, the ANNs were used as an algorithm for mapping the measured data into fault code, which is equivalent to searching the fault dictio- nary performed by some other diagnostic procedures. At the topmost level, the fault dictionary was split into parts simplifying the implementation of the concept. A voting system was created at the topmost level in order to distinguish which ANNs output is to be accepted as the flnal diagnostic statement. The approach was tested on an example of an analog-to-digital converter, and only one test point was used, i.e. the digital output. Full diversity of faults was considered in both digital (stuck-at and delay faults) and analog (parametric and catastrophic faults) parts of the diagnosed system. Special attention was paid to the faults related to the A/D and D/A interfaces within the circuit.

Iddq fault model generation for BiCMOS and CMOS circuits

In this paper, an approach for Iddq test generation for BiCMOS and CMOS VLSI circuits is presented. After a brief review of Iddq testing, basic ideas and general problems in Iddq testing of BiCMOS and CMOS VLSI are given. The application of this method is illustrated on three basic examples for BiCMOS and one for CMOS VLSI circuits. Circuits are simulated on PSpice, and results of these simulations are presented in an appropriate form. Finally, the possibilities for further research in Iddq testing for both BiCMOS and CMOS VLSI circuits are mentioned.

A third order sigma-delta modulator

The design of a sigma-delta modulator is presented in this paper. Third order mash structure is chosen and implemented. Top-down methodology is used and described. Design fulfills imposed requirements which is verified with post-layout transistor level simulation results.

Automatic symbolic analysis of SC networks using modified nodal approach

This paper presents symbolic analysis of Switched-Capacitor (SC) circuits in the z-domain using the Modified Nodal Approach (MNA). The analyses are performed on the SymsimC symbolic simulator, which also enables s-domain network analysis. The results of simulations are demonstrated on practical examples of SC-networks. The influence of finite gain and bandwidth of operational amplifiers on the circuits behaviour is also examined.

Analysis of discretization methods applied on DC-SOGI block as part of SRF-PLL structure

Phase Locked Loop (PLL) is wide used for grid parameters estimation, as well for grid-converters synchronization. Key block at single-phase Synchronous Reference Frame PLL (SRF-PLL) structure is two-phase generator which is used for generation of two quadrature signals, which are necessary for SRF block. One of the issues that could appear during estimation of grid parameters is appearance of DC offset in measured grid voltage. In this paper is described second order generalized integrator (SOGI) which is capable to fully reject DC offset and noise which could appear in measured input grid voltage. This two-phase generator is named DC-SOGI. Analog DC-SOGI is made of two second order filters. While these structures are mostly digitally implemented, then it is interesting to analyze discretization method and sampling time impact on two-phase generator. Simulation results confirm given assumption.

Cell design for boundary-scan implementation

This paper gives a new approach in cell design for boundary-scan implementation. After recalling on major problems in PCBs testing, a short overview of boundary-scan standard is given. Furthermore, logic level synthesis of boundary-scan cells are done. Logic level design of these cells are used for layout generation. From generated layout, netlist for each circuit is extracted, and after that simulated by Alecsis2.4. The simulation results are compared with expected values, and are presented in appropriate manner.