P. Rossel

Avalanche characteristics of MOS transistors

This paper reviews the mechanisms that induce a negative resistance in MOS transistors operating in the avalanche mode. For n-channel devices, it is shown that snapback can be associated with the body effect of the MOS transistor. At high current levels, carrier injection by the source, turn-on of the parasitic n-p-n transistor, and excess carrier charge in the pinched channel are taken into account. Subthreshold currents may also be involved. The associated safe operating area limits are determined analytically. Induced failures in multi-cell power MOSTs are also discussed. An electrical model for the simulation of the device characteristics in the avalanche regime is suggested.

Novel concepts for high voltage junction termination techniques using very deep trenches

Numerous techniques have been used to improve the voltage handling capability of high voltage power devices with the aim to obtain the breakdown of a plane junction. In this work, we present a new high voltage junction termination technique using very deep trenches available from microsystems technologies. This new concept names Trench Termination Technique: T/sup 3/ increase the device breakdown voltage to almost the ideal value of the plane case and, in the same time, consume a much lower Silicon space than the previous proposed solutions as an example. Two different architectures for 6 kV devices are described, but these techniques are easily scalable to any voltage range (in the field of high voltage devices).

A new generation of power devices based on the concept of the "Floating Islands"

In this paper, a new concept called Floating Islands Diode (FLI-Diode) is proposed: the voltage handling capability of this new diode is assumed by the association of several PN junctions in series. This new concept can be applied to any power devices (lateral or vertical): for instance, the specific on-resistance of a 900 Volts Vertical DMOS Transistor is strongly improved (reduction of 70% when compared to the conventional structure).

A new device for smart power integrated circuits - the trench lateral DMOSFET

In this paper, a new concept of lateral DMOSFET for medium voltage (<100 Volts) Smart Power Integrated Circuits is proposed. This structure called LUDMOSFET features a reduced specific on-resistance and enhanced breakdown voltage. For example, for a breakdown voltage of 50 V, the specific on-resistance is 1.2 m/spl Omega/.cm/sup 2/ in the conventional LDMOSFET, 0.8 m/spl Omega/.cm/sup 2/ in the LUDMOS without polysilicon (i.e. 30 percent reduction) and 0.6 m/spl Omega/.cm/sup 2/ in the LUDMOS with polysilicon (i.e. 50 percent reduction).

The on-resistance limits of high cell density power MOSFET's

In this paper, the on-resistance limits of low-voltage power VDMOSFETs and trench power MOSFETs are studied, based on an analytical approach and 2D device modelling. It is shown that, unlike VDMOSFET, the trench MOSFET performance is not limited by the JFET effect. From a theoretical point of view, for N-channel devices, the 60 V optimized trench MOSFET would present a specific on-resistance equal to 0.32 m/spl Omega/.cm/sup 2/ while the equivalent VDMOSFET would present a specific on-resistance of 0.51 m/spl Omega/.cm/sup 2/.

Power MOS devices: structures and modelling

In this paper, the evolution of power MOS transistor structures is presented. Actual devices are described with their respective models. Physical numerical models are detailed together with those intended for circuit simulation.

Advanced concepts in smart power integrated circuits

Industrial Power ICs (Smart Power) are mainly intended for the automotive industry. Usually, they are manufactured using the junction-based isolation technological process. This paper deals with the main elements associated with the future development of this type of circuit. Among the basic issues dealt with are: industrial development, decrease in chip size using submicronic technologies, energy capability and some problems related to electrical isolation.

Limit of D.C. performance of trench power MOSFETs

In this paper, the limit of performance of low-voltage trench power MOSFETs and VDMOSFETs is studied from the points of view of specific on-resistance and cell density. It is shown that unlike VDMOSFET the trench MOSFET is not limited by the JFET effect. From a theoretical point of view, the 60 V trench MOSFET could have an on-resistance equal to 0.4 m/spl Omega/.cm/sup 2/.

Modelling and performance of vertical trench MOSFET in power electronics

In this paper, a family of SPICE models is proposed for the recently developed trench power MOSFET. Our modeling and parameter extraction approach is based on an analytical study, on two-dimensional device simulations and on experimental characterisation. Then, it is shown that regarding the total power losses, the trench MOSFET could be a device of choice, compared with classical high cell density vertical DMOSFET.