F. Morancho

Effect of surface preparation and interfacial layer on the quality of SiO2/GaN interfaces

In this work, SiO2/GaN MOS structures have been fabricated using Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition (ECR-PECVD) for deposition of silicon dioxide (SiO2) at low temperature (300u2009°C) on N-type, NID and P-type GaN epitaxial layers. Surface preparation involving chemical, UV-Ozone oxidation and oxygen plasma oxidation have been investigated by XPS analysis of the GaN surfaces prior to SiO2 deposition. The association of UV ozone and plasma oxidation allows a complete removal of carbon contamination and has a huge beneficial effect on the quality of the SiO2/GaN interface. Electrical C-V characterizations put into evidence the improved quality of the SiO2/GaN interface with a low interface trap density of 1010 cm−2 eV−1. The advantage of this soft interface treatment is thus specially observed for the N-type samples without annealing step, whereas improvements are still needed in the case of NID and P-type samples.

Thermal behavior of a superjunction MOSFET in a high-current conduction

In this paper, a detailed study of the superjunction MOSFET (SJ-MOSFET) thermal behavior on high-current conduction is presented. First, the heat-generation (HG) process and its dependence on device geometry and biasing conditions are elucidated from numerical-simulation tools. Later, the resultant temperature distribution is evaluated by simulation, thus, acquiring a physical understanding of its impact on the electrical characteristics and failure mechanisms, particularly at short-circuit operation. The obtained results show relevant differences with respect to the thermal behavior of conventional power MOSFETs. As a matter of fact, the maximum HG in SJ-MOSFET is found at a certain distance from the surface, which principally depends on the drift length. This fact has important implications on the device reliability prediction and a compact electrothermal modeling

Static and Dynamic Analysis of Split-Gate RESURF Stepped Oxide (RSO) MOSFETs for 35 V Applications

In this work, the static and dynamic performance of three different proposed trench MOSFET architectures for a 35 V breakdown range have been analyzed by means of extensive TCAD simulations. The trench field-plate in the drift region in RSO MOSFET structures highly improves the Ron-sp/VBR trade-off in comparison with the conventional UMOS counterpart. The Split-Gate RSO MOSFET is an alternative solution in order to reduce the gate-to-drain charge and capacitance, therefore further reduce the switching losses with respect to RSO MOSFET.

Behavioral Study of Single-Event Burnout in Power Devices for Natural Radiation Environment Applications

Two-dimensional numerical simulations have been performed to define the sensitive volume and triggering criteria of single-event burnouts (SEBs) for standard and superjunction MOSFETs and planar and trench IGBTs for different configurations of ionizing tracks and for different conditions of polarization and temperature. The analysis of the results gives a better understanding of the SEB mechanism in each structure and a comparison of behavior and robustness of these technologies under heavy-ion irradiation.

Deep trench MOSFET structures study for a 1200 Volts application

In this work we studied some possible high voltage MOSFETs structures that can replace the IGBT in the railway traction converters. In this purpose, some high voltage power MOS structures are presented and theoretically compared using 2D simulations. Simulations results show that the DT-UMOSFET should be a good challenger to the 1200 Volts IGBT. Moreover, the influence of various parameters, like trench width, trench verticality or boron dose, on DT-UMOSFET static performances is shown.

Optimisation of low voltage Field Plate LDMOS transistors

An alternative 3D RESURF method applied in power MOSFETs consists on placing a thick trench oxide of together with a poly-silicon layer inside the trench oxide together with a poly-silicon layer inside the trench along the drift region. The metal-thick-oxide acts as a field-plate (FP), enhancing the 3D RESURF lateral depletion which allows increasing the N-drift doping concentration. The feasibility of applying the FP concept in lateral DMOS devices has been analyzed in this paper by means of 1D analytical formulation, and by extensive 2D and 3D TCAD simulations.

TCAD Simulation of the Single Event Effects in Normally-OFF GaN Transistors After Heavy Ion Radiation

Electrical behavior of normally-off GaN power transistors under heavy ion stress radiation is presented based on 2D-TCAD numerical simulation in order to better understand the mechanism of Single Event Effects (SEE) in this devices.

An improved junction termination design using deep trenches for superjunction power devices

Among the numerous solutions developed to improve the handling capability of superjunction power devices, the Deep Trench Termination (DT2) is the most adapted thanks to its lower cost and size compared to other technologies using the multiple epitaxy technique, and an easier implementation in the fabrication process. This paper presents the optimization of the Deep Trench Termination by means of TCAD 2D and 3D-simulations allowing the realization of deep trench superjunction devices (diodes and MOS transistors) for 1200 V applications. The work is focused on the influence of the dielectric passivation layer thickness and the field plate length on the breakdown voltage of a DT-SJDiode.

Switching performance of 65V vertical N-channel FLYMOSFETs

In this paper, the switching performance of 65V vertical N-channel FLYMOSFETs is investigated for the first time and compared with a conventional vertical DMOSFET (VDMOSFET). It is shown that measurements of the different capacitances and the gate charge of the two devices are comparable. A 2D simulation study of two equivalent structures (i.e. FLYMOSFET and VDMOSFET exhibiting the same breakdown voltage) confirms that floating islands did not cause parasitic or new phenomenon, in the case of weakly doped islands.

Super-Junction PIN Photodiode to Integrate Optoelectronic Integrated Circuits in Standard Technologies: A Numerical Study

The use of super-junction (SJ) techniques in PIN photodiodes is proposed in this letter for the first time with the objective to assist the optoelectronic integrated circuits (OEICs) implementation in complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS) and bipolar-CMOS-double diffused MOS (BCD) technologies. Its technological viability is also discussed to make it credible as an alternative to other OEICs approaches. Numerical simulation of realistic SJ-PIN devices, widely used in high power electronics, demonstrates the possibility to integrate high-performance CMOS-based OEICs in epitaxial layers with doping concentrations above 1×1015 cm-3. The induced lateral depletion at low reverse biased voltage, assisted by the alternated N and P-doped pillars, allows high-speed transient response in SJ-PIN detecting wavelengths between 400 and 800 nm. Moreover, other important parameters as the responsivity and the dark current are not degraded in respect to the conventional PIN (C-PIN) structures.