P. Satish Kumar

A simplified space vector PWM for cascaded H-Bridge inverter including over modulation operation

This paper presents a simplified space vector pulse width modulation method for multilevel inverters. In this method, the desired switching states of the reference voltage vector and switching time calculations are done online through generalized simple expressions without any predetermined data in the memory lookup table. The proposed method is also extended for over modulation region by incorporating the concept of reference voltage vector and ON-time modification. This new control method is attractive in terms of reduction in computational complexity, minimization of voltage and current THD and the extension of range for over modulation operation; the simulation has been carried out for cascaded H-Bridge five level inverter including over modulation range using MATLAB/Simulink. The hardware implementation of the proposed method has been done using XILINX SPARTAN-3A FPGA Processor. The simulation waveforms validate the harmonic analysis of voltage and current at different modulation index.

Comparative analysis of modulation strategies applied to seven-level diode clamped multi-level inverter fed induction motor drive

This paper presents analysis and comparison of most commonly preferred pulse width modulation strategies such as PD, POD, APOD PWMs to control the speed of an induction motor by using seven level diode clamped multilevel inverter. Different multi-carrier PWM techniques are investigated for Voltages, currents, apparent power, active power, reactive power, power factor and THD. Several interesting characteristics of them are shown to help it from using it to renewable, facts, grid connected converter and industrial applications. Results are depicting the effectiveness of control in the motor speed and an enhanced drive performance through reduction in total harmonic distortion (THD). Experimental results obtained from a Hardware setup are presented, confirming the good-quality waveforms with PD-PWM and the adequate balance of all floating capacitors.

FPGA implementation of space vector pulse width modulated Neutral Point Clamped three-level Inverter fed Induction motor drive

This paper is proposed on generating efficient PWM pulses using space vector modulation technique for a three phase three level NPC voltage source inverter fed Induction motor drive using a low cost and an efficient field programmable gate array (FPGA) controller for Industrial application. The space vector modulation technique for three-level NPC inverters using the nearest three Triangle Vectors (NTV) is discussed in detail. The proposed scheme is able to easily determines the location of reference vector and calculation of on times. It uses a simple mapping to generate gating signals for the inverter using Space vector modulation strategy to reduce the THD. The performance of three level inverter is analyzed in terms of line voltages, currents and total harmonic distortion (THD) using both simulation and Hardware implementation for detailed analysis. In the proposed work, SVM algorithm is described in high-speed integrated circuit hardware description language coding and implemented using XILINX SPARTAN 3A DSP FPGA processor. The simulation and Hardware results have been good agreement with the proposed work.

Mapping method based Space Vector Modulation technique for diode clamped multilevel inverters

This paper implements Space Vector Pulse Width Modulation (SVPWM) technique for Five level and Seven level Diode Clamped Inverters (5L-DCMLI and 7L-DCMLI). This technique is based on mapping methods where initially space vector is expressed as sum of a contender vector and an error vector. The contender vector is the one which is nearest to the reference space vector. An error vector is arrived by calculating vector difference of a contender vector from reference vector. The error vector is translated to origin of space vector diagram by using translation methods. For an n-level inverter, there will be (n-1) steps in space vector diagram. Since the amplitude of the error vector will be less than one step of the space vector diagram, two level space vector technique can be applied to it. The switching states thus obtained can be added to contender vector to get a vector which is very close to the reference vector and follows it in time. Simulation is carried out using MATLAB/Simulink and the performance results of SVPWM method of 5L-DCMLI and 7L-DCMLI are presented. The inverter is connected to Induction motor load and performance is evaluated.

Performance analysis of four level NPC and NNPC inverters using capacitor voltage balancing method

Mostly, the conventional neutral point clamped (NPC)multilevel inverters are implemented for odd number of levels in the output. In this paper, four level NPC inverter is implemented and compared with the nested neutral point clamped (NNPC) inverter. The NNPC inverter is a four level inverter for high power applications. This inverter is a combination of diode clamped and flying capacitor multilevel inverters which consists of two flying capacitors in each phase and uses the same voltage rating of diodes. This method is suitable for SPWM and SVM PWM schemes. The inverter is fed to an induction motor load for static and dynamic operations using capacitor voltage balancing method. The performance results of SPWM method of four level NNPC inverter is compared with the four level diode clamped inverter using MATLAB/Simulink. SVM method is also implemented for four level NNPC inverter using various modulation indices and observed that the NNPC inverter has better THD values.

Implementation of FPGA based space vector PWM method for five level cascaded inverter

This paper presents generation of switching pattern using simplified Space Vector Pulse Width Modulation technique and its implementation with FPGA. The proposed modulation method is effective regarding the reduction of computational difficulty and execution time, in calculation of on duration of switches. The switching scheme generates a voltage vector with reduced total harmonic distortion with low switching frequency. This technique is verified for five level Cascaded inverter experimentally and simulated with dynamic model of Induction Motor Load in MATLAB/ Simulink software before implementation. The simulation and experimental results shows that both are in close correspondence.