P. Valente

Development of Network Interface Cards for TRIDAQ systems with the NaNet framework

NaNet is a framework for the development of FPGA-based PCI Express (PCIe) Network Interface Cards (NICs) with real-time data transport architecture that can be effectively employed in TRIDAQ systems. Key features of the architecture are the flexibility in the configuration of the number and kind of the I/O channels, the hardware offloading of the network protocol stack, the stream processing capability, and the zero-copy CPU and GPU Remote Direct Memory Access (RDMA). Three NIC designs have been developed with the NaNet framework: NaNet-1 and NaNet-10 for the CERN NA62 low level trigger and NaNet3 for the KM3NeT-IT underwater neutrino telescope DAQ system. We will focus our description on the NaNet-10 design, as it is the most complete of the three in terms of capabilities and integrated IPs of the framework.

Comparative results on the deflection of positively and negatively charged particles by multiple volume reflections in a multi-strip silicon deflector

Bent silicon crystals in channeling mode are already used for beam extraction and collimation in particle accelerators. Volume reflection of beam particles is more efficient than beam channeling; however, the mean deflection angle is rather small. An experiment on the deflection of a 400 GeV/c proton beam and a 150 GeV/c π− beam at CERN using a multi-strip silicon deflector in reflection mode is described. The mean deflection angle of beam particles has been considerably increased due to sequential volume reflections realized in the deflector. This gives possibility for a successful usage of the multi-strip deflectors for beam collimation in high-energy accelerators.

P326 Photon Vetoes Simulation

The P326 experiment aims to a very rare decay, K+ rarr pi+nunu-, immersed in a overwhelming K+ rarr pi+nu, K+ rarr pi+pi0 (and other decays) background. This calls for an impressive rejection capability (1012) in order to keep a significant signal/background ratio while keeping a good overall efficiency. The detector should then be hermetic to photons in order to have a pi0 inefficiency at the level of 10-8, that translates in an unprecedented single photon inefficiency of 10 -5 (above 1 GeV). The design of such a detector is a challenge both from the instrumental and from the simulation point of view. Three detector elements will cover the P326 experiment acceptance: the liquid krypton calorimeter of NA48, a set of large angle veto rings and small angle counters. In order to control the inefficiency at the level of 10-5, all the uncertainties in the detector response simulation/parametrization should be kept at the same level of accuracy. This calls for very detailed simulation description both at the level of accurate geometry description and of realistic digitization and signal generation. At the same time, in order to carefully check the uniformity of the detector response over the whole acceptance, the mechanical and construction details should be precisely included. Finally, all the physics processes in the materials should be reproduced at the same level of accuracy. A very detailed study of the large angle veto structure exploiting the full potential of the GEANT4 technology has been developed in order to design the detector and to validate the required photon detection inefficiency on real-scale prototypes.

Real-time heterogeneous stream processing with NaNet in the NA62 experiment

The use of GPUs to implement general purpose computational tasks, known as GPGPU since fifteen years ago, has reached maturity. Applications take advantage of the parallel architectures of these devices in many different domains. Over the last few years several works have demonstrated the effectiveness of the integration of GPU-based systems in the high level trigger of various HEP experiments. On the other hand, the use of GPUs in the DAQ and low level trigger systems, characterized by stringent real-time constraints, poses several challenges. In order to achieve such a goal we devised NaNet, a FPGA-based PCI-Express Network Interface Card design capable of direct (zero-copy) data transferring with CPU and GPU (GPUDirect) while online processing incoming and outgoing data streams. The board provides as well support for multiple link technologies (1/10/40GbE and custom ones). The validity of our approach has been tested in the context of the NA62 CERN experiment, harvesting the computing power of last generation NVIDIA Pascal GPUs and of the FPGA hosted by NaNet to build in real-time refined physics-related primitives for the RICH detector (i.e. the Cerenkov rings parameters) that enable the building of more stringent conditions for data selection in the low level trigger.

Experimental apparatus to study crystal channeling in an external SPS beamline

For the new generation of high intensity hadronic machines as, for instance, LHC, halo collimation is a necessary issue for the accelerator to operate at the highest possible luminosity and to prevent the damage of superconductor magnets. We propose an experiment aimed to systematic study of the channeling phenomenology and of the newly observed volume reflection effect. This experiment will be performed for an external SPS beamline and will make use of a primary proton beam with 400 GeV/c momentum and very small (∼ 3 &mgr;rad) divergence. The advantage of a proposed experiment is precise tracking of particles that interacted with a crystal, so that to determine the single-pass effciency for all the processes involved. For this purpose, a telescope equipped with high-resolution silicon microstrip detectors will be used. New generation silicon crystals and an extra-precise goniometer are mandatory issues. Main goal of the experiment is to get the precise information on channeling of relativistic particles and, ultimately, on the feasibility of such technique for halo collimation at LHC. In this contribution we review the status of the setting-up of experimental apparatus and its future development in sight of the planned run in September 2006.