Padmanabhan Balasubramanian

Dual-Sum Single-Carry Self-Timed Adder Designs

This paper presents designs of self-timed dual-sum single-carry or dual-bit adder function blocks, constructed using commercially available synchronous library resources (standard cells) and validated using synchronous tools. Specifically, the proposed adder modules qualify as either quasi-delay-insensitive or speed-independent and satisfy Seitz’s weak-indication timing constraints. The delay-insensitive version of the ripple carry adder topology has been used to analyze the designs. The indication (completion) is either made implicit in the topology (local indication) or considerably isolated from the actual data path (a new variant of global indication). The proposed adders are found to exhibit improved power and performance parameters, whilst being competitive in terms of area, in comparison with those pertaining to other self-timed logic realizations

Synthesis of Power and Delay Optimized NIG structures

Structuring and mapping of a Boolean function is an important problem in the design of digital combinatorial circuits. Library aware constructive decomposition offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-inverter graphs (AIG) [1] [5], NAND graphs, OR-inverter graphs (OIG), AND-XOR-inverter graphs, reduced Boolean circuits [8] does exist in literature. In this work, we discuss a novel efficient synthesis method for combinational logic circuits, represented using a NAND-inverter graph (NIG), which is composed of only two-input NAND (NAND2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive normal forms, comprising terms with minimal cardinality. Construction of a NIG for a non-regenerative function in normal form would be straightforward, whereas for the opposite phase, it would be developed by considering a virtual instance of the function. However, the choice of best NIG for a given function would be based upon node count and cell count needed for actual implementation at the technology independent stage. We compare the power efficiency and delay improvement achieved by optimal NIGs over minimal AIGs and OIGs for some case studies. In comparison with functionally equivalent and redundant AIGs, NIGs report mean savings in power and delay of 33.76% and 18.57% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a similar comparison with OIGs, NIGs demonstrate average savings in power and delay of 45.67% and 20.92% respectively.