Palkesh Jain

Product drift from NBTI: Guardbanding, circuit and statistical effects

Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time, we report a monotonic reduction in variance of the log parameters (Ln(ΔF/F) and Ln(ΔID/ID)) as a function of stress time. A stochastic guard banding model accounting for time-dependent variance, re-ordering effects and granularity of data is demonstrated.

Accurate Current Estimation for Interconnect Reliability Analysis

An improved and efficient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Significantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily configured to work with different combinations of ramp and exponential waveforms. Subsequently, the inadequacies of using conventional EM-severity metrics: either the nets lumped capacitance or the nets effective capacitance, along with the regular timing slew, for EM analysis are outlined. As a correction, and, application of proposed method, we provide formulations for deriving the effective “EM” slew, which can be used with conventional approaches to accurately compute the currents. Further, unlike traditional wisdom, we note that not just the RMS current, but even the total charge transfer can depend on the waveform type, and propose formulations to that regard. Additionally, for the first time, we present a method for incorporating the drivers dynamic IR drop while computing RMS currents. Alongside, we lay recommendations for ensuring the standard-cell EM safety at chip level. Finally, we share model-validation results from a production 40 nm design, enabling a 40% higher performance closure.

New electromigration validation: Via Node Vector Method

Electromigration (EM) is a traditional reliability concern, aggravated recently due to intense shrinking of wire sizes and the increase in the number of interconnections on a system-on-chip (SoC). Thereby, it challenges the state-of-the-art in design, physics, process and CAD processes. To that regard, we propose a new EM check method named Via Node Vector method. The conventional EM check ignores the lead EM interaction in circuits and only checks the local current densities. The new method addresses the EM interactions and checks the EM reliability at the lead connection sites (called via node). It converts the electrical current density of each lead into an effective current density for the EM interaction consideration. For this, we introduce three new factors: length (FL), width (FW), and interaction (FB). The effective current density divergence at a via node is derived as an addition of the effective current densities of all the interacting leads, which is a close proxy to represent the physical atomic flux divergence at the via node. This divergence at a via node can then be readily compared with the technology EM spec. The proposed method is successfully applied to 28nm node IPs and shows up to ∼4X higher safe operating frequency than the conventional method allows. Additionally, it successfully identifies risky sites missed by conventional check. The Via Node Vector Method will provide higher performance with reliability in designing advanced digital and analog circuits.

A systematic approach for analyzing and optimizing cell-internal signal electromigration

Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects, and is used to analyze the lifetime of large benchmark circuits. Further, a method for optimizing the circuit lifetime using minor layout modifications is proposed.

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects

A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and voltage-dependent pin capacitance in the library model. It additionally provides an on-the-fly retargeting capability for reliability constraints by allowing arbitrary specifications of lifetimes, temperatures, voltages, and failure rates, as well as interoperability of the IPs across foundries. The characterization part of the methodology is expedited through the intelligent IP-response modeling. The ultimate benefit of the proposed approach is demonstrated on a 28-nm design by providing an on-the-fly specification of retargeted reliability constraints. The results show a high correlation with SPICE and were obtained with an order of magnitude reduction in the verification runtime.

Reducing the signal Electromigration effects on different logic gates by cell layout optimization

In modern integrated circuits, the Electromigration (EM) effects are not just seen on power delivery networks. EM is also an increasing problem in the internal metal wires of cells, referred as cell-internal signal Electromigration. In this work we present a detailed analysis of the cell-internal signal Electromigration effects considering different logic gates. The lifetime optimization by placing the output pin of the gates is dependent of the output wire shape and the logic of the gate. We are also presenting ways to improve the lifetime of the cells optimizing the cell layout.

Stochastic and topologically aware electromigration analysis for clock skew

An important link between individual component-level EM failures and the failure of the associated system is established in this work. Conventional EM methodologies are based on the weakest link assumption, which deems the entire system to fail as soon as the first component in the system fails. With a highly redundant circuit topology - that of a clock grid - we present algorithms for EM assessment, which allow us to incorporate and quantify the benefit from system redundancies. We demonstrate that unless such an analysis is performed, chip lifetimes are underestimated by over 2x.

A retargetable and accurate methodology for logic-IP-internal electromigration assessment

A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization- and reuse-based, and naturally incorporates complex effects such as clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition.

Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs

A detailed introduction to the problem of asymmetric aging of mixed signal CMOS circuits is given in this paper, with special focus on clock skew, pulse width, and aspects of burn-in. A comprehensive look into the origin and aggravation of the problem due to power management techniques is presented. Additionally, various asymmetric aging analyses and management techniques, including conventional timing analysis frameworks, are shared. For the first time, problem formulation and desensitization schemes in a statistical framework are presented. Subsequently, design guidelines are shared that can be applied on production clock designs to significantly alleviate the asymmetric aging problem. Several of these techniques must be applied to advanced production designs to enable higher performance and integrity.