Srikanth Krishnan

A comprehensive framework for predictive modeling of negative bias temperature instability

A quantitative model is developed for the first time, that comprehends all the unique characteristics of NBTI degradation. Several models are critically examined to develop a reaction/diffusion based modeling framework for predicting interface state generation during NBTI stress. NBTI degradation is found to be dominated by diffusion of neutral atomic and molecular hydrogen related defects. Additionally, the presence of hydrogen gettering sites such as unsaturated grain bound- aries significantly enhance NBTI degradation, whereas hydrogen sources reduce NBTI degradation. The model also suggests the possible mechanisms for saturation. The model is calibrated over a range of stress temperatures and voltages. The model captures recovery, experimental delay and frequency effects successfully.

Impact of negative bias temperature instability on digital circuit reliability

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.

NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

We describe a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications. Mobility degradation is shown to be a significant (/spl sim/40%) contributor to I/sub D/ degradation. We report for the first time, degradation in gate-drain capacitance (C/sub GD/) due to NBTI. The impact of this C/sub GD/ degradation on circuit performance is quantified for both digital and analog circuits. We find that C/sub GD/ degradation has a greater impact on the analog circuit studied than the digital circuit. We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom. Further, a numerical model based on the reaction-diffusion theory has been developed, which is found to satisfactorily describe degradation, recovery and post-recovery response to stress.

Material dependence of hydrogen diffusion: implications for NBTI degradation

Negative bias temperature instability (NBTI) is known to exhibit significant recovery upon removal of the gate voltage. The process dependence of this recovery behavior is studied by using the time slope (n) as the monitor. We observe a systematic variation of n with oxide thickness, nitrogen concentration, and fluorine implantation. Incorporation of the material dependence of the diffusivity within the reaction-diffusion (R-D) framework captures the observed trends. The consequences of this modification are (a) diffusion limitation is shown to arise from diffusion in poly-Si, rather than oxide, (b) a plausible explanation for low-voltage stress induced leakage current (LV-SILC) naturally appears. Important findings are (a) NBTI degradation remains significant at high frequencies, (b) numerical simulations at moderate frequencies can be used to predict circuit impact in the GHz regime, (c) high frequency operation can be modeled as a lower effective DC stress

Negative bias temperature instability mechanism: The role of molecular hydrogen

The role of dimerization of atomic hydrogen to give molecular hydrogen in determining negative bias temperature instability (NBTI) kinetics is explored analytically. The time dependency of NBTI involving molecular hydrogen was found to obey a power law with a slope of 1∕6, as opposed to the 1∕4 slope derived for a reaction involving atomic hydrogen. The implications of this dimerization reaction for voltage and temperature acceleration are also discussed. Simulation results validating these predictions are also described. The higher slopes typically reported for NBTI are shown to be an artifact of measurement, and experimental data supporting this lower time dependency is shown.

Statistical prediction of circuit aging under process variations

Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on compact models of transistor degradation and circuit performance, we develop analytical solutions that efficiently predict the statistics of both circuit timing and the leakage under temporal stress and process variations. These solutions prove that circuit aging and its variance can be fully predicted from the characteristics of transistor degradation and circuit performance sensitivity to aged parameters, independent on the type and the amount of process variations. Specific results include: (1) under variations, the standard deviation of circuit speed declines with the stress time, following a power law of 1/6; and (2) the logarithmic mean and the standard deviation of leakage current decrease with the stress time as t1/6. The results are systematically validated by simulation and measurement data from an industrial 65 nm technology, enhancing the predictability and efficiency of statistical reliability analysis.

Atomic-Scale Defects Involved in the Negative-Bias Temperature Instability

This paper examines the atomic-scale defects involved in a metal-oxide-silicon field-effect-transistor reliability problem called the negative-bias temperature instability (NBTI). NBTI has become the most important reliability problem in modern complementary-metal-oxide-silicon technology. Despite 40 years of research, the defects involved in this instability were undetermined prior to this paper. We combine DC gate-controlled diode measurements of interface-state density with two very sensitive electrically detected magnetic-resonance measurements called spin-dependent recombination (SDR) and spin-dependent tunneling (SDT). An analysis of these measurements provides an identification of the dominating atomic-scale defects involved in NBTI in pure- and plasma-nitrided oxide (PNO)-based devices. We are also able to observe atomic-scale defects involved in HfO2-based devices (although a definitive identification of the dominating defects structure was not possible). Our results in pure- devices indicate an NBTI mechanism which is dominated by the generation of Pb0 and Pb1 interface-state defects. (Pb0 and Pb1 are both silicon dangling-bond defects, in which the central silicon is back-bonded to three other silicon atoms precisely at the interface). This observation is consistent with what most NBTI researchers have assumed. However, our observations in PNO devices contradict with what most NBTI researchers had previously assumed. We demonstrate that the dominating NBTI-induced defect in the plasma-nitrided devices is fundamentally different than those observed in pure-based devices. Our measurements indicate that the new plasma-nitrided NBTI-induced defects physical location extends into the gate dielectric. The defect participates in both SDR and SDT. Our SDR results strongly indicate that the plasma-nitrided defect has a density of states which is more narrowly peaked than that of centers and is near the middle of the band gap. The high sensitivity of our SDT measurements allow an identification of the physical and chemical nature of this defect through observations of hyperfine interactions. The defects are silicon dangling bonds, in which the central silicon is back-bonded to nitrogen atoms. We call these NBTI-induced defects centers because of the similarities to the centers observed in silicon nitride (the silicon-nitrided center is also a silicon dangling bond in which the silicon atom is back-bonded to nitrogen atoms). The defect identification in plasma-nitrided devices helps to explain the following phenomena: (1) NBTIs enhancement in plasma-nitrided devices; (2) conflicting reports of NBTI-induced interface states and/or bulk traps; and (3) fluorines ineffectiveness in reducing NBTI in plasma-nitrided devices. We also observe the atomic-scale defects involved in NBTI in HfO2-based devices and find that short- and long-term stressing generates different defects and that these defects are different than those observed in the SiO2 and plasma-nitrided devices. Our results also suggest that the NBTI-induced defects in these devices are physically located in the interfacial layer (not at the interface).

Circuit aging prediction for low-power operation

Low-power circuit operations, such as dynamic voltage scaling and the sleep mode, pose a unique challenge to aging prediction. Traditional aging models assume constant voltage and averaged activity factor, ignoring the impact of the long sleep period, and thus, result in a significant overestimation of the degradation rate. To accurately predict the aging effect in low-power design, this work first examines critical model assumptions in the reaction-diffusion process that is responsible for the NBTI effect. By using the correct diffusion profile, it then proposes a new aging model that effectively analyzes the degradation under various low-power operations. The new model well predicts the aging behavior of scaled CMOS measurement data (45nm and 65nm) with different operation patterns, especially sleep mode operation and dynamic voltage scaling. Compared to previous aging models, the new result captures the essential role of the long recovery phase in circuit aging, reducing unnecessary guardbanding in reliability protection.

off -State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.