Panagiotis Linardis

Efficient static compaction of test sequence sets through the application of set covering techniques

The test sequence compaction problem is modelled here, as a set covering problem. This formulation enables the straightforward application of set covering methods for compaction. Because of the complexity inherent in the first model, a second more efficient, formulation is proposed where the test sequences are modelled as matrix columns with variable costs (number of vectors). Further, matrix reduction rules appropriate to the new formulation, which do not affect the optimality of the solution, are introduced. Finally, the reduced problem is minimized with a branch & bound algorithm. Experiments on a large number of test sets show significant reductions to the original problem by simply using the presented reduction rules. Experimental results comparing our method with others form the literature and also with the absolute minima of the examples, computed separately with the MINCOV algorithm, support the potential of the proposed approach.

An audio signatures indexing scheme for dynamic content multimedia databases

This paper describes a method of content indexing for dynamic multimedia databases using binary signatures of the audio signals. The analysis scheme focuses on the audio objects of the multimedia environment, extracts semi-stationary audio segments and analyzes their key features, These are: the fundamental frequency F0, the first three formants F1, F2, and F3, the associated phoneme and speaker identification information. Binary signatures are associated with the audio segments which they describe. For each audio segment these key features are encoded within the signature and information retrieval can be performed on the multimedia database querying the corresponding signatures of the streamed audio. The signature structure serves as an index of the associated audio objects assisting their retrieval.

Accelerating the compaction of test sequences in sequential circuits through problem size reduction

The problem of compacting a set of test sequences for sequential circuits is modeled here with the help of a covering matrix, where the test sequences are modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults. From this formulation, reduction rules are extracted, particular to this type of problem which, iteratively applied, result in a significant reduction of the size of the initial compaction problem. A characteristic of the reduction rules is that their application will not compromise the optimum solution of the problem. The remaining reduced problem is then solved by a combination of a heuristic and an exact branch and bound algorithm. Experimental results using the above reduction rules show that the sizes of the given sets of test sequences are often significantly reduced and many times these rules directly produce the absolute minimum of the solution. The final results, compared with others from the literature and also with the absolute minima of the examples, computed separately, support the potential of the proposed approach.

Interpretation of Byzantine music notation as adaptive /spl Delta/-modulation

This paper presents a model for encoding the Byzantine music notation. The analysis is performed by inventing a universal code according to the model of PCM adaptive modulations and especially /spl Delta/ modulation. The proposed code is modular and can be used compressed or stripped for the analysis of musical notation as a morphogenetic field while fully augmented it serves as a musical interface capable of reproducing Byzantine melodies in solfege or instrumental mode. Such an execution can be achieved by special computer programs-synthesizers developed in our department that employ as basis for their interpretation algorithms the proposed encoding-decoding methodology scheme.

PARCIS: a robust parallel VLSI circuit simulator

Abstract The accurate verification of VLSI circuits is essential for their successful and economic production but is an extremely time consuming process for the large circuits of today. This paper describes a robust parallel circuit simulator, PARCIS, designed for a message passing multiprocessing system. It uses a demand driven technique, based on the analysis of hierarchically partitioned circuits. The computation time is reduced by decoupling the circuit equations and distributing the computational load over many processors. On each processor, the circuit blocks, compacted in hierarchical levels, are analyzed asynchronously according to their temporal activity. Currently the PARCIS system is running on a network of transputers. To demonstrate the effectiveness of the proposed simulation program, results are presented for the simulation of typical digital circuits, showing that the execution time decreases in a constant rate as the number of processors (transputers) increases.

Modelling and navigating space-time drift of digitized radar rainfall patterns

Abstract A navigation model is developed and used to account for the horizontal drift of the falling radar rainfall patterns due to wind. In addition to the horizontal displacement of the radar rainfall field, the model also computes the time required by a raindrop to reach the ground from the level that is detected by radar. A bivariate statistical objective analysis is used as a basis for comparison. An error statistic is computed to evaluate the performance of the navigation model. The results indicate that the horizontal displacement of the rainfall field ranges between 1 and 4 km, and the time required by a rain particle to reach the ground varies from 1 to 4 min. The effect of the model on horizontal displacement decreases with increasing integration time and area size.