Michael G. Dimopoulos

Wavelet Analysis for the Detection of Parametric and Catastrophic Faults in Mixed-Signal Circuits

Methods for testing both parametric and catastrophic faults in analog and mixed-signal circuits are presented. They are based on the wavelet transform (WT) of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform. The tolerance limit, which affects fault detectability, for the good or reference circuit is set by statistical processing data obtained from a set of fault-free circuits. In the wavelet analysis, two test metrics, one based on a discrimination factor using normalized Euclidean distances and the other utilizing Mahalanobis distances, are introduced. Both metrics rely on wavelet energy computation. Simulation results from the application of the proposed test methods in testing known analog and mixed-signal circuit benchmarks are given. In addition, experimental results from testing actual circuits and from production line testing of a commercial electronic circuit are presented. These results show the effectiveness of the proposed test methods employing the two test metrics against three other test methods, namely, a test method based on the root-mean-square value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum, and a method based on the WT of the measured signal.

Efficient static compaction of test sequence sets through the application of set covering techniques

The test sequence compaction problem is modelled here, as a set covering problem. This formulation enables the straightforward application of set covering methods for compaction. Because of the complexity inherent in the first model, a second more efficient, formulation is proposed where the test sequences are modelled as matrix columns with variable costs (number of vectors). Further, matrix reduction rules appropriate to the new formulation, which do not affect the optimality of the solution, are introduced. Finally, the reduced problem is minimized with a branch & bound algorithm. Experiments on a large number of test sets show significant reductions to the original problem by simply using the presented reduction rules. Experimental results comparing our method with others form the literature and also with the absolute minima of the examples, computed separately with the MINCOV algorithm, support the potential of the proposed approach.

An evolutionary method for efficient computation of mutual capacitance for VLSI circuits based on the method of images

Abstract The problem of computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is studied in this work. The proposed method is an approximate extended version of the method of images. The initial problem is formulated here as an optimization problem for the solution of which a genetic algorithm (GA) is employed. The proposed method is fast, general, does not rely on fitting techniques and is applicable to an arbitrary 2D or 3D geometry configuration of conductors. Extensive simulation results are presented for several practical case studies. Comparative results are given with other methods from literature and a commercial tool employing the Finite Element Method (FEM). The results show that the capacitance value computed by our method is in close agreement to the value obtained by the other methods from literature and also by the commercial tool with the average difference ranging between 2% and 5% while demonstrating better scalability as the problem complexity rises.

Prospects of 3D inductors on through silicon vias processes for 3D ICs

Three dimensional (3D) integration attempts to keep Moores Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

Design and development of a versatile testing system for analog and mixed-signal circuits

In this paper the design and development of a test system based on a microcontroller is presented. This system is versatile to test various analog and mixed-signal systems without any hardware modification. Preliminary results from the application of the system to the production line testing of emergency light products are presented showing the effectiveness of the proposed testing scheme.

Circuit Implementation of a Supply Current Spectrum Test Method

A supply current spectrum test method is developed in this work, and its implementation using measurements of various analog circuits is presented. Statistical data from fault-free circuits are effectively exploited to compute tolerance limits that affect fault detectability. A low-cost microcontroller-based measuring system that was designed and utilized for mixed-signal fault detection in production line and used for the application of the proposed method is briefly described. For exploitation of combinations of test methods, time consumption considerations are given to derive conditions under which a test method can effectively be used as a preprocessing step before another more time-consuming test method. Experimental results demonstrating the effectiveness of the proposed supply current test method are presented.

Accelerating the compaction of test sequences in sequential circuits through problem size reduction

The problem of compacting a set of test sequences for sequential circuits is modeled here with the help of a covering matrix, where the test sequences are modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults. From this formulation, reduction rules are extracted, particular to this type of problem which, iteratively applied, result in a significant reduction of the size of the initial compaction problem. A characteristic of the reduction rules is that their application will not compromise the optimum solution of the problem. The remaining reduced problem is then solved by a combination of a heuristic and an exact branch and bound algorithm. Experimental results using the above reduction rules show that the sizes of the given sets of test sequences are often significantly reduced and many times these rules directly produce the absolute minimum of the solution. The final results, compared with others from the literature and also with the absolute minima of the examples, computed separately, support the potential of the proposed approach.

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip

An online fault tolerant routing algorithm for 2D mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime permanent and temporary failures that may result in message corruption, message loss or deadlocks, the routing algorithm is enhanced with packet retransmission and a new message recovery scheme. Simulation results, for various network sizes, different traffic patterns, under an unconstrained number of node and link faults, temporary and/or permanent, demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies. As the experiments have shown, the proposed algorithm maintains high reliability of more than 97.68% for a 2D mesh network of 16x16 and in the presence of 384 simultaneous link faults. For the same network and in the extreme scenario of 103 routers being simultaneously faulty, the obtained reliability is more than 93.40%.

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.

Simulation and measurements for testing an emergency luminaire circuit

In this paper simulation and measurements used for testing an emergency luminaire are presented. Model validation is accomplished by comparing the PSpice data with the experimental data acquired with the help of an oscilloscope and a measuring system which offers real-time storage of current and voltage waveform measurements. Simulations of the fault-free circuit and faulty circuit instances proved to be in good accordance to the measured data. From the simulated fault-free and several commonly encountered faulty circuit cases, a fault dictionary can be built in order to be used in a fault circuit diagnosis method for emergency luminaire circuits.