Paolo Canestrari

Optimization of partial coherence for half-micron i-line lithography

A wide range of partial coherences is explored in order to clarify their real impact on lithographic latitude of different kinds of patterns. The effects of coherence variations on process characteristics are reported in terms of exposure latitude and focus budget. It is shown that the use of a particular coherence, different from the standard one, can practically benefit the latitude of a critical layer such as the contact mask.

IDEAL double exposure method for polylevel structures

IDEAL has been proposed as a new double exposure technique to realize k1 equals 0.3 optical lithography. We have applied this technique to complicated 2D structures that can be found in a poly-level of a memory test pattern device. Experimental results showed that IDEAL has a quite large process window also on structured substrate such as SiN and poly-silicon. For the CD target of 0.13 micrometers , exposure latitude larger than 10 percent with a depth of focus larger than 0.5 micrometers was achieved by IDEAL exposure. The alignment latitude of the two reticles used to compose the final lithographic image was larger than +/- 40 nm, moreover line-end shortening effects are also improved by IDEAL exposure.

248 nm Lithography for 180 nm contact holes

In this paper we describe the use of 248 nm lithography to define 0.18 @mm contact holes. For this application we evaluated two Attenuated Phase Shifting Masks (APSM) with transmission 3 and 6 %, in combination with a resist commonly used for binary mask applications. The side lobe effect, that normally limits the lithographic process window in the APSM applications, was decreased by means of a contact hole geometry such as to improve the diffraction pattern. Simulation results and printed wafers confirmed the validity of this approach.

Impact of reticle defects on submicron 5x lithography

During past years a lot of efforts were put from several authors in order to approach the problems related to reticle defect printability. Several works analized the physical phenomena affecting the mask imperfection reproducibility and recently it was showed that the impact of reticle defects eeems to increase by going from micron to submicron lithography. The goal at the base of the present work has been to verify these hypothesis by starting from the experience collected in the previous works and by designing targeted experiments in order to classify the real critical impact of the possible important factors.

Demonstration of production readiness of an immersion lithography cell

This paper describes the qualification work performed on a state-of-the-art immersion cluster and shows results for an immersion process for the 45nm node. These results demonstrate full compliance with all lithographic parameters, including CD control and defectivity. Qualification was performed on an RF3iTM wafer track from Sokudo Co., Ltd. and a 1.2NA immersion scanner. A three-layer material stack was engineered using 820Å BARC / 1800Å ArF photoresist covered by 900Å immersion top-coat. After verification of tool and process cleanliness and testing the robustness of the material stack for use in the immersion scanner, resulting photo cell monitor (PCM) defect density on a 65nm memory device was evaluated. Critical dimension was verified using both CD-SEM and optical CD metrology. Results on a 45nm L/S pattern showed 0.55nm WIW 3sigma CD uniformity using optical CD metrology. Lot to lot CD control was tested for being below 1.5nm 3sigma. As special Soak-units were used prior to post exposure bake (PEB), the influence of post exposure delay (PED) on the CD performance was studied and quantified. All immersion-related modules were optimized and qualified on both 65nm products and 45nm prototypes. Additionally, comparison data for immersion and dry lithography will be presented.

Direct measurement of stepper mark detection accuracy on processed wafers

A novel method to evaluate the accuracy of the stepper alignment system on processed substrates has been developed. The technique allows one to measure directly, with a limited number of wafers and high accuracy, just the contribution of the alignment system inaccuracy to final overlay. Applications of the method are under evaluation, especially in the optimization of the alignment systems of steppers. Experimental procedures and algorithms are provided and some examples of experimental results are shown.

Near and sub-half-micrometer geometry SEM metrology requirements for good process control

Over the past ten years lpw kV Electron Microscopy has been the technique of choice for inprocess, critical layer metrology, for leading-edge design-rule devices. However, conventional low kY Secondary Electron microscopy is reaching its limits in its ability to measure near and sub-half micron features at all levels due to charging issues and interpretation of resist profile. A re-evaluation of the strategy for determining CD measurement site becomes increasingly important as site to site differences are more significant at these smaller dimensions. Otherwise an apparently well controlled process measured in a typical site (e.g. array of a memoiy cell) could be failing due to shorts in critical sites. These critical sites tend to challenge the limits of conventional SEM metrology more. A new generation of SEMs offering a variety of techniques to overcome these limitations has recently arrived on the market, these improve visibility and reduce the effects of charging, allowing a more accurate and representative control ofa lithographic process to be made.

On wafer measurement of mask-induced overlay error

In this paper we present the results of an evaluation into the effects of mask unflatness on the overlay budget. We have investigated two different situations: firstly the case of a single sided telecentric lens and secondly that of a double telecentric one. The results have been determined by measuring this effect directly on wafer.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Process-induced wafer distortion: its measurement and effects on overlay in stepper-based advanced lithography

The distortion introduced by some manufacturing steps on wafers can sometimes have a strong effect on overlay results. Thermal processes, for example, can introduce wafer distortions that cannot be completely compensated by the stepper alignment system with a consequent degradation in overlay. A new methodology which can measure the process induced distortion on wafers (exposed with a stepper system) at different steps in a standard process flow has been developed and is described in this paper. This method does not require any external metrology instruments apart from a standard precision stepper and the method is compatible with all process layers. Experimental results of application of the method on manufacturing process are presented.

Qualification of tools for overlay measurement on processed wafers

Abstract In this paper we present two new methodologies to verify the accuracy of a measurement tool. The dependence of the measurements on substrates and the correlation with the same patterns with the same misalignment is shown. Theusefulness and reliability of the methods is proved by examples on commercially available equipment.