Paolo Cusinato

Analysis of the behavior of a dynamic latch comparator

This brief deals with the behavior of a dynamic latch used as a voltage comparator. A detailed analysis of the fine settling phase is reported, putting in evidence the non-idealities which lead to comparison errors. A technique to minimize such errors is suggested. An experimental chip has been fabricated and measurements are reported and discussed.

Reducing the power consumption in high-speed /spl Sigma//spl Delta/ bandpass modulators

Power consumption is a key point in the design of high-speed switched capacitor (SC) circuits, which efficiently implement a number of analog functions. Among them, SC EA modulators are very popular for analog-to-digital conversion. In this kind of circuit, operational amplifiers are the most consuming cells because of their requirements in terms of dc-gain and unity-gain frequency. An operational amplifier with 90 dB de-gain and a unity-gain frequency of 250 MHz is presented. The large power consumption (18 mW) could make critical its use in commercial applications, in particular for portable devices. However, combining this cell with a fast adaptive biasing circuit, high performance may be achieved with a 40% power consumption reduction. This approach has been used in the design of a sixth-order bandpass /spl Sigma//spl Delta/ modulator suitable for the conversion at intermediate frequency (10.7 MHz) of the FM radio signal. A comparison with a structure without the proposed solution demonstrates that the modulator performance are not degraded by the proposed technique.

A compact-disc analog-to-digital front-end in BiCMOS technology

A BiCMOS analog front-end to be used in a complete two-chip set with a digital signal processor for compact disc (CD) applications is presented. The proposed device exchanges data with the digital counterpart by means of a I2C-like bus serial interface. Four input signals (currents or voltages) are preamplified with flat group-delay and digitized with 6-bit (for servo path) and 6-bit (for RF path) accuracy. This accuracy is achieved without using an equalizer in the signal path. The system is designed to process CD signal with speed up to 4/spl times/ (i.e. 3.2 MHz bandwidth). The device is realized in a 0.7 /spl mu/m BiCMOS technology using 21.5 mm/sup 2/ chip area.

A CD analog front–end in BiCMOS technology

A BiCMOS analog front-end to be used in a complete two-chip set with a digital signal processor for Compact Disk (CD) is presented. The proposed device exchanges data with the digital counterpart by means of a I2C-like bus serial interface. Four input signals (current or voltage) are preamplified with flat group-delay and digitized with 6-bit (for servo path) and 8-bit (for RF path) accuracy. This accuracy is achieved without using an equalizer in the signal path. The system is designed to process CD signal with speed up to 4x (i.e. 3.2MHz bandwidth). The device is realized in a 0.7µm BiCMOS technology using 21.5mm2chip area.

An analog VLSI massively parallel module for low-level cortical processing in machine vision

A new approach to analog VLSI implementations of algorithms for visual cortical processing is presented. Specifically, we introduce a massively parallel architecture, organized as a planar resistive network with voltage controlled current generators locally connected to model interaction schemata responsible for specific sensitivities in cortical neurons. We demonstrate the feasibility of this approach by designing and simulating 24/spl times/24 node analog modules implementing Gabor-like oriented receptive fields, that can be used in machine vision real time systems to evidence texture differences.

Digital Technique for Instability Detection and Saturation Recovery in High-Order SC ΣΔ Modulators

Stability and saturation recovery are a key concern in High-order Switched Capacitor (SC) ΣΔ modulators, since they are conditionally stable architectures.A novel digital technique, which allows to detect instability in the digital domain, a fast recover of high-order modulators from instability and guarantees a minimum of Signal-to-Noise Ratio (SNR) also when the architecture gets unstable, is proposed. This technique operates in two steps: first, the instability is detected in the digital domain and the system is recovered to a proper operation and then a digital post-processing is performed in order to achieve a residual SNR also in the instability condition.This strategy has been applied to a 6th-order SC bandpass ΣΔ modulator operating at 42.8 MHz and featuring 74 dB Dynamic Range (DR) in a 200 kHz bandwidth. The benchmark modulator has been integrated in a standard double-poly 0.35 μm 3.3 V CMOS technology with five metal layers.

Power consumption reduction in high-speed /spl Sigma//spl Delta/ bandpass modulators

Power consumption is a key point in the design of high-speed switched capacitor (SC) circuits, which allow to efficiently implement a number of analog functions. Among them, SC &Sgr;Δ modulators are very popular for A/D conversion: in this kind of circuits, operational amplifiers are the most consuming cells because of their requirements in terms of DC gain and unity-gain frequency. A new amplifier with 110dB DC gain and a unity-gain frequency of 250MHz is presented. The large power consumption (20mW) makes critical its use in commercial applications: however, combining this cell with a fast adaptive biasing circuit, high performance may be achieved with a reasonable dissipation. This approach has been used in the design of a 6th-order bandpass &Sgr;Δ modulator featuring 73dB DR and suitable for the conversion at IF (10.7MHz) of the FM radio signal.

Saturation recovery technique for high-order bandpass switched capacitor /spl Sigma//spl Delta/ modulators

This paper focuses on the topic of /spl Sigma//spl Delta/ modulators stability and saturation recovery for high-order Switched Capacitor (SC) structures. A technique, which allows a fast recover of the modulator from instability (<300ns) and guarantees a minimum of 20dB SNR also when the architecture gets unstable, is proposed. This technique is based on two steps: (1) instability detection with system recovery and (2) digital post-processing. This strategy has been applied to a 6th-order SC bandpass /spl Sigma//spl Delta/ modulator operating at 42.8MHz with 74dB Dynamic Range (DR). The proposal is validated by extended experimental results.