Franco Maloberti

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

Curvature-compensated BiCMOS bandgap with 1-V supply voltage

In this paper we present a bandgap circuit capable of generating a reference voltage of 0.54 V. The circuit, implemented in a submicron BiCMOS technology, operates with a supply voltage of 1 V. In the bandgap circuit proposed we use a non-conventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1 V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 5 ppm / K of accuracy without requiring additional operational amplifiers or complex circuits.

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the implementation of large-time constants both linearized operational transconductance amplifiers with reduced transconductance and impedance scalers schemes for grounded capacitors are employed. Experimental results for the filter have shown a dynamic range (DR) of 60 dB, while the harmonic distortion components are below -50 dB. The power consumption for the filter is below 10 /spl mu/W, the power supply is /spl plusmn/1.5 V, and the active area is 1 mm/sup 2/. The filter was fabricated in a double poly double metal 0.8 /spl mu/m CMOS process.

Modeling sigma-delta modulator non-idealities in SIMULINK(R)

This paper presents a complete set of SIMULINK(R) models, which allow exhaustive behavioral simulations of any sigma-delta modulator to be performed. The proposed set of models takes into account most of the sigma-delta modulator non-idealities, such as sampling jitter, kT/C noise and operational amplifier parameters (noise, finite gain, finite bandwidth, slew-rate and saturation voltages). For each model we present a description of the considered effect as well as all of the implementative details. Simulation results on a second-order switched-capacitor sigma-delta modulator demonstrate the validity of the models proposed.

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator

The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

Two-dimensional magnetic microsensor with on-chip signal processing for contactless angle measurement

The reported CMOS microsystem is the key element for accurate angle measurements. In combination with a permanent magnet, it is used for various wear free angular positioning control systems for automotive and industrial applications covering the full 360/spl deg/ range. The integrated system includes a two-dimensional (2-D) magnetic microsensor (30/spl times/30 /spl mu/m/sup 2/ active area), offset compensation, and signal conditioning circuitry. A novel approach for the angle calculation is presented using an on-board incremental ADC. A bitstream representing the angular position of the applied permanent magnet is provided at the system output. The system achieves a 1/spl deg/ angular resolution with 9 mW power consumption and a permanent magnet of 100 mT. The chip is fabricated in a generic 2-/spl mu/m, double-poly, double-metal CMOS process and covers an area of 2.6/spl times/4.1 mm/sup 2/.

A single-chip optical sensor with analog memory for motion detection

A 64/spl times/64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-/spl mu/m standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm/sup 2/. >

A direct-digital synthesizer with improved spectral performance

The authors present a modified direct-digital synthesizer which uses noise shaping to reduce the effects of phase-accumulator truncation on the output spectrum. The discrete spectral disturbances associated with this truncation error are strongly reduced with the proposed method, making the synthesizer suitable for high-performance signal processing. The proposed architecture uses first-order noise shaping. Higher order noise shaping can also be used if required. The modified circuit offers considerable improvement in the synthesizer performance when the generated frequency is low with respect to the clock frequency. >

A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications

This paper presents a novel two-stage low dropout regulator (LDO) that minimizes output noise via a pre-regulator stage and achieves high power supply rejection via a simple subtractor circuit in the power driver stage. The LDO is fabricated with a standard 0.35mum CMOS process and occupies 0.26 mm2 and 0.39mm2 for single and dual output respectively. Measurement showed PSR is 60dB at 10kHz and integrated noise is 21.2uVrms ranging from 1kHz to 100kHz

A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter

A single-inductor dual-output DC-DC buck converter is presented. The inductor, which is external, provides two independent output voltages ranging from 1.2V to the power supply with a maximum total output current of 200mA. The supply can range from 2.6 to 5V. The converter is fabricated in a 0.35mum p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved and the efficiency is always >62.5%.