Pascal Giard

Fast Polar Decoders: Algorithm and Implementation

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.

Fast List Decoders for Polar Codes

Polar codes asymptotically achieve the symmetric capacity of memoryless channels, yet their error-correcting performance under successive-cancellation (SC) decoding for short and moderate length codes is worse than that of other modern codes such as low-density parity-check (LDPC) codes. Of the many methods to improve the error-correction performance of polar codes, list decoding yields the best results, especially when the polar code is concatenated with a cyclic redundancy check (CRC). List decoding involves exploring several decoding paths with SC decoding, and therefore tends to be slower than SC decoding itself, by an order of magnitude in practical implementations. In this paper, we present a new algorithm based on unrolling the decoding tree of the code that improves the speed of list decoding by an order of magnitude when implemented in software. Furthermore, we show that for software-defined radio applications, our proposed algorithm is faster than the fastest software implementations of LDPC decoders in the literature while offering comparable error-correction performance at similar or shorter code lengths.

Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes

In this paper, we present hardware and software implementations of flexible polar systematic encoders and decoders. The proposed implementations operate on polar codes of any length less than a maximum and of any rate. We describe the low-complexity, highly parallel, and flexible systematic-encoding algorithm that we use and prove its correctness. Our hardware implementation results show that the overhead of adding code rate and length flexibility is little, and the impact on operation latency minor compared with code-specific versions. Finally, the flexible software encoder and decoder implementations are also shown to be able to maintain high throughput and low latency.

Increasing the speed of polar list decoders

In this work, we present a simplified successive cancellation list decoder that uses a Chase-like decoding process to achieve a six time improvement in speed compared to successive cancellation list decoding while maintaining the same error-correction performance advantage over standard successive-cancellation polar decoders. We discuss the algorithm and detail the data structures and methods used to obtain this speed-up. We also propose an adaptive decoding algorithm that significantly improves the throughput while retaining the error-correction performance. Simulation results over the additive white Gaussian noise channel are provided and show that the proposed system is up to 16 times faster than an LDPC decoder of the same frame size, code rate, and similar error-correction performance, making it more suitable for use as a software decoding solution.

237 Gbit/s unrolled hardware polar decoder

In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput of over 237 Gbps for a (1024,512) polar code implemented using an FPGA. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.

Implementation of a Differential Chaos Shift Keying communication system in GNU radio

In this paper the first experimental chaos radio system using Differential Chaos Shift Keying is realized. The software design and implementation are proposed for the experimental Differential Chaos Shift Keying (DCSK) system on software defined radio (SDR) to perform in a real-time wireless transmission. The GNU Radio platform is used as a flexible and open-source platform for our implementation. In order to perform in real-time wireless scenarios, the proposed work implements a synchronization unit on the receiver side. Since our system is on a SDR, the bitrate, bandwidth and central frequency can be modified at ease. The experimental performance are discussed and compared to the theoretical predictions. Finally some trends concerning implementation are discussed.

Design of a New Differential Chaos-Shift-Keying System for Continuous Mobility

Conventional differential chaos-shift-keying systems (DCSK) are not the most suitable for supporting continuous-mobility scenarios. Therefore, in this paper an improved continuous-mobility differential chaos-shift-keying system (CM-DCSK) is presented that provides greater agility and improved performance in fast fading channels without accurate channel estimation while still being simple compared to a conventional DCSK system. A new DCSK frame signal is designed to reach this goal. In our new frame design, each reference sample is followed by a data carrier sample. This modification of the system design reduces the hardware complexity of DCSK because it requires a shorter wideband delay line and significantly improves the performance over fast fading channels while keeping the non-coherent nature of the transmission system. Once the design is explained, the bit error rate performance is computed over a multipath fast fading channel and compared to the conventional DCSK system. Simulation results confirm the advantages of this new noncoherent spread-spectrum design that can support mobility.

Autogenerating software polar decoders

Polar decoders are well suited for high-speed software implementations. In this work, we present a framework for generating fully-unrolled software polar decoders with branchless data flow. We discuss the memory layout of data in these decoders and show the optimization techniques used. At 335 Mbps, when decoding a (2048, 1707) polar code, the resulting decoder has more than twice the speed of the state of the art floating-point software polar decoder.

FPGA implementation and evaluation of discrete-time chaotic generators circuits

In this paper, implementation of discrete-time chaotic generators widely used in digital communications is studied and evaluated. The study focuses on power consumption, resource usage, and maximum execution frequency of implementations for two common Field Programmable Gate Arrays (FPGAs). While the Bernoulli map ranks first in all three aspects, results show significant ranking differences among the other chaotic generators. Results were obtained by first implementing the chaotic generators in a high level register to transistor level description language and then using tools from FPGA manufacturers to obtain the resource usage as well as estimate the other desired characteristics.

Low-Latency Software Polar Decoders

Polar codes are a new class of capacity-achieving error-correcting codes with low encoding and decoding complexity. Their low-complexity decoding algorithms rendering them attractive for use in software-defined radio applications where computational resources are limited. In this work, we present low-latency software polar decoders that exploit modern processor capabilities. We show how adapting the algorithm at various levels can lead to significant improvements in latency and throughput, yielding polar decoders that are suitable for high-performance software-defined radio applications on modern desktop processors and embedded-platform processors. These proposed decoders have an order of magnitude lower latency and memory footprint compared to state-of-the-art decoders, while maintaining comparable throughput. In addition, we present strategies and results for implementing polar decoders on graphical processing units. Finally, we show that the energy efficiency of the proposed decoders is comparable to state-of-the-art software polar decoders.