Pascal Salome

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process

ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.

Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network

This work focuses on interconnect heating during fast ESD transients. A simplified thermal RC network is used to study the behavior of interconnects and to predict their failures, which can be an open circuit or a latent failure due to the decrease in electromigration lifetime. The RC model is validated by both experiments and finite difference simulations. We observe that the melting of the interconnect system can be considered to be instantaneous. Simulations in both solid and liquid phases of the metal are in good agreement with experiments. Human body model (HBM) and machine model (MM) transients are investigated and a relationship to correlate these ESD stresses with transmission line pulse (TLP) measurements is studied in depth. We show that a square pulse of 80 ns may be used to predict HBM stress and a 45 ns pulse is proposed for MM stress.

A new multi-finger SCR-based structure for efficient on-chip ESD protection

This paper introduces a new SCR-based (silicon controlled rectifier) structure for on-chip ESD protection. The STMSCR (smart triggered multi-finger SCR) relies on the bimodal operation of a LSCR (lateral SCR) using an external triggering circuitry that permits switching from a transparency mode to a protection mode as soon as an ESD event is detected. The trigger voltage can be adjusted by design without any impact on the ESD performance. The STMSCR is multi-finger compliant, thus allowing area-efficient design of pad-located ESD protection. The STMSCR is demonstrated in a 0.18 μm CMOS technology without any process customization; an HBM failure threshold over 115 V/μm is reached while always ensuring current uniformity in multi-finger structures.

An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures.

This work focuses on the thermal soft failure mechanism happening in NMOS transistors during low level ESD stresses. Soft and Hard failure modes are both precisely characterized using Atomic-Force Microscopy (AFM) technique. Thermally induced soft failures are shown to be the first step of the hard failure mechanism. Furthermore, a strong relationship between both soft and hard failures is revealed. Contrary to what was reported until now, our investigation underlines the presence of two different hot spots during the formation of the large melted silicon filament leading to the disastrous short circuit called hard failure.

Extended SPICE-like model accounting for layout effects on snapback phenomenon during ESD events

Abstract An extended SPICE-like model for snapback phenomenon including the impact of gate length and substrate on the holding voltage is presented. Substrate conduction is analytically solved thanks to a transmission line model. A fast extraction methodology is also described. This model is in good agreement with the measurements performed on deeply submicron CMOS technologies.

ElectroStatic discharges (ESD), latch-up and pad design constraints

This paper is tailored to beginners in the field of electrostatic discharges. After a brief introduction, the basics of ESD are first reviewed and followed by a description of the standards devoted to the protection of intregrated circuits. Then, the behavior and modeling of elementary devices under ESD are discussed.