C. Richier

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process

ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.

Study of the ESD behavior of different clamp configurations in a 0.35 μm CMOS technology

At present, submicron technologies, electrostatic discharges (ESD) are one of the major threats to the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifinger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human body model (HBM) and charged device model (CDM) test results, as well as transmission line measurement (TLM) and light emission results support this finding.

Extended SPICE-like model accounting for layout effects on snapback phenomenon during ESD events

Abstract An extended SPICE-like model for snapback phenomenon including the impact of gate length and substrate on the holding voltage is presented. Substrate conduction is analytically solved thanks to a transmission line model. A fast extraction methodology is also described. This model is in good agreement with the measurements performed on deeply submicron CMOS technologies.

ElectroStatic discharges (ESD), latch-up and pad design constraints

This paper is tailored to beginners in the field of electrostatic discharges. After a brief introduction, the basics of ESD are first reviewed and followed by a description of the standards devoted to the protection of intregrated circuits. Then, the behavior and modeling of elementary devices under ESD are discussed.

Comparison of different on-chip ESD protection structures in a 0.35 μm CMOS technology

In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifinger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human Body Model (HBM) and Charged Device Model (CDM) test results, as well as Transmission Line Measurement (TLM) and light emission results support this finding.

Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress.

The main purpose of this article is to present some silicon signatures induced by electro-static discharge (ESD) stresses and to propose to approach it with 2D and 3D TCAD simulations and under simplifying assumptions. All test chips are stressed by Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Moreover each stress is performed on one chip only to avoid cumulative silicon signatures. It appears that the substrate current induced by any of these stresses leads to the same damage on silicon. Thus, HBM, MM and CDM have a common failure and silicon signature. Moreover the information of the Failure Analysis (FA) only cannot provide an exclusive conclusion in term of ESD stress. Also this kind of local stress can be considered as a latent default for the ESD reliability of devices by oxide overstress and/or charge trapping and/or contact impact and/or STI impact.