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New Product Development Visualization & Optimization using DSMs

Where task dependencies are sufficiently complex, process-architecture or task-based Design Structure Matrices (DSMs) can be used to visualize, analyze and optimize those dependencies.This paper explores integrated circuit (IC) new product development (NPD) visualization and optimization (i.e. make more predictable) using such DSMs.First, an initial, non-optimized, DSM is constructed that reflects typical feedforward dependencies derived from integrated circuit development experience and worst-case feedback dependencies derived from potential unplanned iterations (UPIs) what-if analysis.This worst-case starting point is then modified to construct a multiple (two) design/layout iteration version, thereby transforming most of the important feedback dependencies into feedforward ones.Additionally, by explicitly integrating both requirements management and risk management tasks into the NPD DSM, a more predictable and optimized NPD task sequence may be determined.

Task Dependency Risk Visualisation using DSMs

Where task dependencies are sufficiently complex, process-architecture or task-based Design Structure Matrices (DSMs) can be used to visualize, analyse and optimize those dependencies. Traditionally, this is done without consideration of task dependency risk. This paper explores a new way to visualize task dependency risk using DSMs. Both feedback path and feedforward path task dependencies are considered with a view to risk rating reduction and risk rating enhancement respectively. By taking task dependency risk rating into consideration, a more optimized taskbased DSM sequence, from an overall schedule risk perspective, may be determined.

Cellular radio linear codec

Designed specifically to satisfy the European cellular radio market, the ADSP28msp02 combines 16-bit A/C, 16-bit D/A with the appropriate anti-aliasing anti-imaging filtering. Fabricated in a VLSI digital process with high linearity poly-poly capacitors, the msp02 contains >100 K transistors in an area >54 K sq. mils with a die aspect ratio allowing the part to be assembled in a 24-pin skinny package while running off a single 5 V supply. Two versions of the linear codec were fabricated and assembled-a monolithic, fully-integrated part and a compound-monolithic, two-chip solution to facilitate investigation into the interaction between the digital and the analog circuitry.<<ETX>>