Patrick Adde

New architecture for high data rate turbo decoding of product codes

This paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innovative circuit architecture stores several data at the same address and performs parallel decoding to increase the data rate. It is able to process several data simultaneously with one memory (classical designs require m memories); its latency decreases when the amount of data processed simultaneously is large. We present results on block turbo decoder designs of 2-data, 4-data and 8-data decoders (where 2, 4 and 8 are the number of data symbols processed simultaneously). For each decoder circuit, the latency is decreased, the area of the processing unit is increased by a factor m and the critical path and memory size are constant (the data rate is increased by m/sup 2/ if we have m parallel decoders).

Performance and complexity of block turbo decoder circuits

This paper presents the latest results on block turbo codes and also an analysis of the possible implementations of a block turbo decoder circuit. Simulation results show that the SNR (signal to noise ratio) required to achieve a BER (Bit Error Rate) of 10/sup -5/ with block turbo codes is 2.5/spl plusmn/0.2 dB from their Shannon limit for any code rate. We have identified three different solutions for implementing the block turbo decoder circuit. After discussing the advantages and disadvantages of the different solutions, we give the results of the degradation of the performance of the block turbo decoder circuit due to data quantization. Finally, in our conclusion, we discuss how to reduce the complexity of the algorithm for its implementation.

An overview of turbo codes and their applications

More than ten years after their introduction, turbo Codes are now a mature technology that has been rapidly adopted for application in many commercial transmissions systems. This paper provides an overview of the basic concepts employed in convolutional and block turbo codes, and review the major evolutions in the field with an emphasis on practical issues such as implementation complexity and high-rate circuit architectures. We address the use of these technologies in existing standards and also discuss future potential applications for this error-control coding technology

A very low complexity block turbo decoder for product codes

This paper presents a low complexity block turbo decoder for product codes. This new decoder, which has been derived from the near-optimum block turbo decoder is a very good compromise between complexity and performance. For performance evaluation, we have considered the [BCH(64,57,4)]/sup 2/ product code transmitted over a Gaussian channel using a QPSK modulation. The complexity of the new block turbo decoder is about ten times less than that of the near-optimum block turbo decoder for a coding gain degradation of only 0.7 dB.

Design and performance of a product code turbo encoding-decoding prototype

This paper presents the latest results on a block turbo decoder design. We propose a block turbo decoder circuit for the error protection of small data blocks such asAtm cells on anAwgn (additive white Gaussian noise) channel with a code rate close to 0.5. A prototype was developed atEnst Bretagne. It allowsBer (bit error rate) measurements down to 10−9 and uses programmable gate arrays (Fpga Xilinx circuits). The elementary extendedBch code and the data block size can be modified to fit specifications of different applications.RésuméCet article présente les derniers résultats concernant un turbo décodeur de code en blocs. Un circuit turbo décodeur permet la correction d’erreurs dans de petits blocs de données tels que ceux utilisés pour les cellulesAtm avec un rendement proche de 0,5. Une maquette a été développée à l’Enst Bretagne simulant un canal gaussien. Elle permet de mesurer de faibles taux d’erreurs binaires (jusqu’à 10−9) et utilise des circuits intégrés programmables (circuits Xilinx). Le codeBch étendu utilisé comme code élémentaire pour le turbo code et la taille du bloc de données peuvent être modifiés afin de les adapter à différentes applications.

Reed-Solomon turbo product codes for optical communications: from code optimization to decoder design

Turbo product codes (TPCs) are an attractive solution to improve link budgets and reduce systems costs by relaxing the requirements on expensive optical devices in high capacity optical transport systems. In this paper, we investigate the use of Reed-Solomon (RS) turbo product codes for 40 Gbps transmission over optical transport networks and 10 Gbps transmission over passive optical networks. An algorithmic study is first performed in order to design RS TPCs that are compatible with the performance requirements imposed by the two applications. Then, a novel ultrahigh-speed parallel architecture for turbo decoding of product codes is described. A comparison with binary Bose-Chaudhuri-Hocquenghem (BCH) TPCs is performed. The results show that high-rate RS TPCs offer a better complexity/performance tradeoff than BCH TPCs for low-cost Gbps fiber optic communications.

A highly parallel Turbo Product Code decoder without interleaving resource

This article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26)2 BCH product code, synthetized in a 90 nm CMOS technology, the resulting information throughput is 2.5 Gb/s with an area of 233 Kgates. Finally a second architecture enhancing parallelism rate is described. The information throughput is 33.7 Gb/s while an area estimation gives A=10 mum2.

Some Results on the Binary Minimum Distance of Reed-Solomon Codes and Block Turbo Codes

We study the minimum distance of the binary expansion of high-rate Reed-Solomon (RS) codes and product codes in the polynomial basis and show that the binary codes obtained in this way usually have minimum distance equal to the designed symbol minimum distance. We then show that a judicious choice for the code roots may yield binary expansions with larger binary minimum distance and better asymptotic performance. This result is used to design high-rate RS product codes with significantly lower error floors compared to classical constructions.

How we implemented block turbo codes

This paper presents a block turbo decoding algorithm, from its theory to its implementation in a programmable circuit. In this study, we discuss the two prototypes realized. It will be possible to compare the complexity of the core of the process, which is the elementary decoder, thanks to the choice of essential parameters. One prototype is more dedicated to high data rates, the other one being implemented on only one FPGA which means a gain in terms of area.First, we briefly focus on the description of the siso (Soft-In Soft-out) algorithm used to implement the turbo decoder. Then, we explain the essential choices in order to adapt the algorithm for an ASIC implementation, which leads to a compromise between area and binary error rate. Finally, we present the two prototypes implemented and their experimental results.RésuméL’objectif de cet article est de présenter le turbodecodage de codes produits depuis la théorie jusqu’à la réalisation sur circuit programmable. Deux prototypes ont été réalisés, Us serviront de support à cette étude. Il sera en effet possible de comparer la complexité du décodeur élémentaire en fonction d’un certain nombre de paramètres, de mettre face à face une structure dédiée aux débits élevés et une structure optimisée en surface.Dans une première partie, on trouvera une brève description de l’algorithme srso (Soft-In Soft-Out) permettant de réaliser le turbo décodage. Vient ensuite la description de l’adaptation de cet algorithme à l’implantation sur silicium. Cette phase nécessite des choix entre complexité en terme de circuit et performance en terme de taux d’erreurs binaires. La dernière partie présente les choix d’architectures et les résultats expérimentaux des 2 prototypes.

Design and implementation of a soft-decision decoder for Cortex codes

Cortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simulation results show that the proposed algorithm achieves an excellent trade-off between performance and complexity for short Cortex codes. A decoder architecture for the (32,16,8) Cortex code based on the (4,2,2) Hadamard code has been successfully designed and implemented on FPGA device. To our knowledge, this is the first efficient digital implementation of a soft-decision Cortex decoder.