Patrick Harvey-Collard

High-Fidelity Single-Shot Readout for a Spin Qubit via an Enhanced Latching Mechanism

The readout of semiconductor spin qubits based on spin blockade is fast but suffers from a small charge signal. Previous work suggested large benefits from additional charge mapping processes, however uncertainties remain about the underlying mechanisms and achievable fidelity. In this work, we study the single-shot fidelity and limiting mechanisms for two variations of an enhanced latching readout. We achieve average single-shot readout fidelities > 99.3% and > 99.86% for the conventional and enhanced readout respectively, the latter being the highest to date for spin blockade. The signal amplitude is enhanced to a full one-electron signal while preserving the readout speed. Furthermore, layout constraints are relaxed because the charge sensor signal is no longer dependent on being aligned with the conventional (2, 0) - (1, 1) charge dipole. Silicon donor-quantum-dot qubits are used for this study, for which the dipole insensitivity substantially relaxes donor placement requirements. One of the readout variations also benefits from a parametric lifetime enhancement by replacing the spin-relaxation process with a charge-metastable one. This provides opportunities to further increase the fidelity. The relaxation mechanisms in the different regimes are investigated. This work demonstrates a readout that is fast, has one-electron signal and results in higher fidelity. It further predicts that going beyond 99.9% fidelity in a few microseconds of measurement time is within reach.

A silicon nanocrystal tunnel field effect transistor

In this work, we demonstrate a silicon nanocrystal Field Effect Transistor (ncFET). Its operation is similar to that of a Tunnelling Field Effect Transistor (TFET) with two barriers in series. The tunnelling barriers are fabricated in very thin silicon dioxide and the channel in intrinsic polycrystalline silicon. The absence of doping eliminates the problem of achieving sharp doping profiles at the junctions, which has proven a challenge for large-scale integration and, in principle, allows scaling down the atomic level. The demonstrated ncFET features a 10{sup 4} on/off current ratio at room temperature, a low 30 pA/μm leakage current at a 0.5 V bias, an on-state current on a par with typical all-Si TFETs and bipolar operation with high symmetry. Quantum dot transport spectroscopy is used to assess the band structure and energy levels of the silicon island.In this work, we demonstrate a silicon nanocrystal Field Effect Transistor (ncFET). Its operation is similar to that of a Tunnelling Field Effect Transistor (TFET) with two barriers in series. The tunnelling barriers are fabricated in very thin silicon dioxide and the channel in intrinsic polycrystalline silicon. The absence of doping eliminates the problem of achieving sharp doping profiles at the junctions, which has proven a challenge for large-scale integration and, in principle, allows scaling down the atomic level. The demonstrated ncFET features a 104 on/off current ratio at room temperature, a low 30 pA/μm leakage current at a 0.5 V bias, an on-state current on a par with typical all-Si TFETs and bipolar operation with high symmetry. Quantum dot transport spectroscopy is used to assess the band structure and energy levels of the silicon island.

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO2, SiO2, HfO2, Al2O3, or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300&#-80;C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.