Patrick Heyne

Read latency control circuit

Semiconductor memory having a delay locked loop

Circuit configuration for enabling a clock signal in a manner dependent on an enable signal

Synchronous integrated memory

Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device

Voltage generator with superimposed reference voltage and deactivation signals

Method and circuit arrangement for resetting an integrated circuit

Integrated circuit for generating a phase-shifted output clock signal from a clock signal

Method and logic/memory module for correcting the duty cycle of at least one control/reference signal

Integrated circuit having adjustable delay units for clock signals