Patrick J. Quinn

Accuracy limitations of pipelined ADCs

In this paper, the key characteristics of the main errors which affect the performance of a switched capacitor pipelined ADC are presented and their effects on the ADC transfer characteristics demonstrated. Clear and concise relationships are developed to aid optimized design of the pipeline ADC and error bounds are derived.

Smart AD and DA converters

In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance mixed-signal cores in VLSI chips. On the other hand, a trend of increasing digital processing power can be observed in almost all these systems. The presented smart approach takes full advantage of this trend in order to solve the before mentioned problems and to achieve true system integration.

A binary-to-thermometer decoder with built-in redundancy for improved DAC yield

This paper describes an architecture for binary-to-thermometer decoders used in segmented D/A converters. To improve basic converter characteristics, the architecture features redundant output thermometer code. The main concept offers two modes of operation. Each mode generates a different thermometer output, i.e. a different switching sequence for the DAC MSB thermometer analog elements. This results in two different transfer characteristics of the whole DAC for the same mismatch errors of its elements. After on-chip or off-chip measurements, the more linear transfer characteristic can be selected. In this way, chip yield is improved and the design requirements can be relaxed. Ultimately, the advantages introduced by the proposed decoder lead to cheaper and smaller D/A converters

A start-up calibration method for generic current-steering D/A converters with optimal area solution

This paper presents a new start-up calibration method for current-steering D/A converters, based on a 1-bit ADC. The paper proposes a new current cell that allows calibration of non-identical current sources by way of a shared calibration apparatus. The current cell uses parallel self-calibrated unit elements. Each of these is calibrated individually and when all combined together, the accuracy of the current sources is improved. This method is independent of the DAC architecture and hence an extra degree of design freedom exists. A minimal area solution can be found through optimizing the calibration strength, since the method is not only applicable to the identical thermometer current sources of the segmented DACs. A general discussion on the new calibration method is offered and conclusions are drawn.

Parallel current-steering D/A Converters for Flexibility and Smartness

This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of available operating modes (op-modes) can set the overall DAC performance and functionality. These op-modes transfer some of the important design trade-offs to the end-user and constitute the DAC flexibility. The main examples include: resolution-power-number of DACs, static-dynamic performance, etc. Secondly, specific signal processing techniques become possible. The main examples of such techniques include: full self-calibration, cancellation of harmonic distortion (HD) components, and linearity improvement through redundancy. This paper concentrates on a method to suppress undesired HD components through DA processing of phase shifted replicas of the main input signal. The presented theoretical concepts are realized in a 14-bit DAC built from 4 parallel 12-bit sub-DACs. Transistor simulations and a layout design are also presented. The demonstrated flexibility characteristics of the new DAC architecture make the discussed concepts particularly suitable for FPGA integration.

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approach is generally employed. The three most significant bit (MSBs) are implemented as seven unary D/A cells and the three least significant bits (LSBs) as three binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5 kb is placed on-chip, which is externally loaded in a serial way but internally read in an 8× time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output nonlinearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC Spurious Free Dyanmic Range >40 dB bandwidth is 0.8 GHz, while the IM3 <;-40 dB bandwidth exceeds 1.3 GHz. The DAC consumes 53 mW of power and the design-for-test scheme -80 mW.

Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs

In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADC. The paper continues by analyzing the optimal design for low power of the scaled back-end stages. Finally, a model is proposed to estimate the power per stage, and hence total power consumption of the pipeline ADC.

A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz

This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range >50 dB can be maintained up to 1 GHz, while keeping the DAC footprint small -0.035 mm2. Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm2. It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost.

A flexible 12-bit self-calibrated quad-core current-steering DAC

This paper presents a flexible fully integrated self-calibrated quad-core 12-bit current-steering 180 nm CMOS DAC. Its novel architecture features multiple parallel sub-DAC unit cores. Their various combinations deliver smart flexibility in: performance, functionality, power management, design reuse, and smartness. The parallel sub-DAC units can be used together or separately to optimize the performance of a targeted mixed-signal application. Unused sub-DAC units can be switched off to optimize the power consumption. The new parallel sub-DACs architecture facilitates a new calibration algorithm. This algorithm together with small calibrating DACs and a current comparator enables the realization of the first fully integrated self-calibration start-up method that corrects the mismatch errors of all binary and unary current sources. The presented self-calibrated flexible DAC achieves measured linearity of better than 12-bit, while occupying small silicon area due to the intrinsic 9-bit accuracy of the DAC unit core.

Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion

A novel implementation for algorithmic and pipelined ADCs is presented in this paper. A floating voltage hold buffer is proposed which enables the accurate addition of signal voltages without requiring precisely matching and linear components. A new 1.5-bit stage is presented based on the floating hold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3.3 MS/s algorithmic ADC in 0.25μm standard CMOS for a 2V application is described. It occupies O.15mm2 of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit algorithmic ADC stages.