A. Farcy

High frequency characterization and modeling of high density TSV in 3D integrated circuits

High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D chip staking are presented in this paper. Works focus on high density TSVs, up to 106 cm−2, with pitch below 10 µm and aggressive wafer thinning to maintain TSV aspect ratio in a range between 5 and 10. Equivalent electrical RLCG models of TSVs with height of 15 µm and diameter of 3 µm are extracted up to 20 GHz. It is shown that values extracted for components are directly related to design and material characteristics used to process 3D TSVs.

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits

Through Silicon Via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more and more mandatory. In this paper, a full parametric and frequency dependent model of high aspect ratio TSV is proposed based on both electromagnetic (EM) simulations and RF measurements. This model enables to extract TSV resistance, self inductance, oxide capacitance and parasitic elements due to the finite substrate resistivity. Its full compatibility with SPICE solvers allows the investigation of TSV impact on circuit performance.

Investigation on TSV impact on 65nm CMOS devices and circuits

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.

Development and characterisation of a 3D technology including TSV and Cu pillars for high frequency applications

As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously. Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, including mobile phones, due to their very high compacity and integration capabilities. Those components need to work at high frequency, typically up to 1 GHz. For these frequencies, the resistance and the capacitance of the interconnections have to be minimized, in order to decrease the signal delay. This is a real challenge for 3D integration and especially for post process through silicon vias. In the first part of the paper, a study and a simple model to determine the main parameters responsible for resistance and parasitic capacitance variation will be presented. Then, a technical focus will be done on the improvement of the TSV electrical performances, especially the decreasing of the TSV parasitic capacitance from 2.41 pF to 0.76 pF based on Plasma Enhanced Chemical Vapour Deposition (PECVD) process development. Finally, the integration of this new material on a technological test vehicle with electrical results will be presented and discussed.

An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation

In this paper, using the new generation of model for assessment of CMOS technologies and roadmaps software, we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation, and variability, such as loaded ring-oscillator delay, as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%-per-year delay improvement to construct a new industrially viable roadmap.

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

Evaluation of Through Silicon Via (TSV) electrical parameters is mandatory to improve heterogeneous 3D chip performance in the frame of a “more than Moore” roadmap. Accurate modeling of TSV is consequently essential to perform design, material and process optimizations. This paper presents a frequency dependent analytical model including MOS effect of high aspect ratio TSV achieved in a full CMOS 65 nm platform according to a face-to-face Via Last process. Specific test structures with bulk contacts to polarize silicon were integrated enabling C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed and simplified according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) leading to a full analytical model.

Development and characterisation of high electrical performances TSV for 3D applications

Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to : • Decrease the form factor of the final system • Improve the thermal and electrical performances of the device • Decrease the cost of the final product In order to stack the heterogeneous components in the third dimension, TSV (Through Silicon Vias) is a very promising technology compare to wire bonding. In this paper, the technological bricks specifically developed for 3D integration demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1] [2]. This flow needed to develop specific wafer level packaging technologies such as: • Top chip & bottom chip interconnections • High aspect ratio TSV included into the bottom wafer • Backside interconnections for subsequent packaging step • Temporary bonding and debonding of bottom wafer [3] [4] • Top chip stacking on bottom wafer In the first part of the paper, the complete process flow will be presented. Then, a technical focus will be done on the specific steps developed for the improvement of the TSVs electrical performances. Finally, the electrical results achieved on a specific test vehicle, similar to the demonstrator will be discussed. The electrical results obtained on a technological test vehicle will be firtly presented. Those results include electrical continuity, pillars resistance, TSV resistance and capacitance and TSV insulation and current losses. Then, the electrical results obtained with the “high electrical performances” process on the functionnal demonstrator will be showed, including a specific focus on the TSV capacitance measurements.

Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.