Paul Anthony Totta

Spalling of Cu6Sn5 spheroids in the soldering reaction of eutectic SnPb on Cr/Cu/Au thin films

The growth and morphology of intermetallic compounds between the solder and substrate play an important role in the solderability and reliability of electronic solder joints. Solder on thin films, as in chip joint, acts as an electrical and mechanical/physical interconnection between the chip and the substrate. We have studied the interfacial reactions between eutectic SnPb (63Sn37Pb, wt%) and Cr/Cu/Au thin films. Our results found here have been compared to the solder reaction on bulk Cu. The eutectic solder has 7° of wetting angle on Cr/Cu/Au thin films rather than 11° on Cu substrate. Sideband around the solder cap was found in both the thin film case and the Cu case. Spalling of Cu6Sn5 compound grains occurred in the thin‐film case when the Cu film was consumed but not in the case of bulk Cu. We observed a shape change from hemispherical ‘‘scallops’’ to spheroids before spalling took place. The shape change is assisted by ripening a reaction among the scallops. We have calculated a critical size of th...

Ripening‐assisted asymmetric spalling of Cu‐Sn compound spheroids in solder joints on Si wafers

In reacting eutectic SnPb solder with Ti/Cu and Cr/Cu/Au thin film metallization on Si wafers, we have observed spalling of Cu6Sn5 spheroids when the solder consumes the Cu. The formation of the spheroids is assisted by the ripening reaction among the compound grains. In addition we have observed an asymmetric spalling phenomenon using a sandwich structure, in which two wafers were soldered face‐to‐face. The spalling occurs predominantly at the interface at the bottom of the solder joint. It suggests that gravity plays a role.

Chip-To-Package Interconnections

Integration of circuits to semiconductor devices, driving the need for improvements in packaging, has been discussed in Chapter 7,“Microelectronics Packaging—An Overview. ” This is further illustrated in Figure 8-1, wherein the cost of interconnecting on silicon is compared with interconnecting on ceramic substrates and on organic boards, clearly showing the lower cost of interconnecting on silicon [1]. Although the trend is toward total integration on Si there is, however, a practical, growing limit to the number of circuits which can be made on a single piece of silicon, which is currently at about 1.6 million circuits for CMOS logic, 40,000 circuits for bipolar logic, and 64 megabits for memory. The highest integrated transistor counts are approximately 5 million on advanced microprocessors. Therefore, because most current information systems require a greater number of circuits and interconnections, a number of chips still need to be interconnected on organic or ceramic first-level packages. The electrical connections between the chip and the package, referred to here as chip-level interconnections, are the subject matter of this chapter. Because, for the systems considered here, no first-level package can usually accommodate all the required chips, a second-level package interconnecting the first levels is often required. These interconnections, referred to as package-to-board interconnections, are reviewed in Chapter 16. A recent deviation from this packaging pattern, also to be discussed, is the direct surface mounting of flip chips on FR4 cards or flexible circuits which is referred to as direct chip attach (DCA) or chip-on-board (COB).

Microstructures of phased-in Cr–Cu/Cu/Au bump-limiting metallization and its soldering behavior with high Pb content and eutectic PbSn solders

The microstructure of phased-in Cr–Cu/Cu/Au multilayer thin films and their solderability with high Pb-content PbSn solder (95/5%) and eutectic PbSn solder (37/63%) were studied by using cross-sectional transmission electron microscopy and scanning electron microscopy. We found that the phased-in Cr–Cu layer is intermixed and grains of both Cr and Cu are elongated along the growth direction. This special compositionally graded or functionally graded microstructure presents a lock-in effect of the Cr and Cu grains. It has succeeded in preventing the spalling of Cu3Sn in solder joints formed using the 95/5% solder, but failed in preventing the spalling of Cu6Sn5 in those formed using the eutectic solder. We suggest that the difference may be due to the different dissolution rates of the two compounds in the solders.

Dewetting of molten Sn on Au/Cu/Cr thin‐film metallization

On Au/Cu/Cr thin film surface, a drop of molten Sn first spreads out to wet the surface, but it then pulls back to dewet. The latter is due to the spalling of Cu–Sn compounds and exposing the Cr surface to the molten Sn when all of the Cu film has been consumed by the wetting reaction. Dewetting is clearly undesirable for solder joints in electronic packaging; the phenomenon is presented here.

Thin film interactions of Al and Al(Cu) on TiW

Thin‐film reactions of Al/Ti22W78 (∼10 wt. % Ti) with and without ∼2 at. % Cu in the Al were investigated by transmission electron microscopy for vacuum annealing in the temperature range 300–600 °C. The reactions are nonuniform and the presence of Cu has little effect on the reaction kinetics. Reactions are grain boundary dominated and start at 400 °C with the formation of WAl12.

Advancing the state of the art in high-performance logic and array technology

High-speed silicon bipolar technology continues to meet the demands of integrated circuits for mainframe computers. IBIVI has developed an advanced bipolar logic and highspeed array technology for Its Enterprise System/9000TM systems. This technology, codenamed ATX-4, is composed of trench-Isolated, doubie-polyslilcon self-aligned bipolar devices, and has four fully pianarized wiring levels with interievel connecting studs. Chip fabrication has been implemented In l-fxm ground rules and Is In full-scale manufacturing. ATX-4 represents a significant advance in providing higher-speed and lower-power logic at increased levels of integration compared with that of the ATX-1 technology used In previous generations. An overview of the design and integration of ATX-4 Is discussed.

History of Flip Chip and Area Array Technology

The concept of interconnecting a chip to a package in a face-down or “flip chip” orientation is simple enough, and forty years old. The idea of having input-output connections all over the face of a flip chip is also a simple idea, and twenty-five years old. Then, how is it, in the last days of the twentieth century, that the electronics industry finds itself in the midst of a revolution in electronic assembly referred to as flip-chip area-array packaging?