Paul E. Landman

Architectural power analysis: The dual bit type method

This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The dual bit type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSBs), but also for the correlated activity of the most significant bits (MSBs), which contain twos-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%. >

High-level power estimation

The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area, but also on power throughout the entire design process. In order to evaluate how well a particular design variant meets power constraints, engineers often rely on CAD tools for power estimation. While tools have long existed for analyzing power consumption at the lower level of abstraction-e.g. SPICE and PowerMill-only recently have efforts been directed towards developing a high-level power estimation capability. This paper surveys the state of the art in high-level power estimation, addressing techniques that operate at the architecture, behavior, instruction, and system levels of abstraction.

Activity-sensitive architectural power analysis

Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criterion. As such there is a growing need for tools that can accurately predict power consumption early in the design process, many high-level power analysis models do not adequately model activity, however, leading to inaccurate results. This paper describes an activity-sensitive power analysis strategy for datapath, memory, control path, and interconnect elements. Since datapath and memory modeling has been described in a previous publication, this paper focuses mainly on a new Activity-Based Control (ABC) model and on a hierarchical interconnect analysis strategy that enables estimates of chip area as well as power consumption. Architecture-level estimates are compared to switch-level measurements based on net lists extracted from the layouts of three chips: a digital filter, a global controller, and a microprocessor. The average power estimation error is about 9% with a standard deviation of 10%, and the area estimates err on average by 14% with a standard deviation of 6%.

Power estimation for high level synthesis

Techniques for rapidly and accurately estimating power consumption based on high level descriptions of system architectures are described. This approach, based on stochastic modeling of bus statistics, achieves the accuracy traditionally associated with gate and circuit level estimation tools while exploiting the reduced computational complexity offered by the architectural level of abstraction. The results presented indicate an estimation accuracy within 9.4% of gate level simulations, while existing high level techniques can be off 80% or more.<<ETX>>

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.

Activity-sensitive architectural power analysis for the control path

Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing need for tools that can accurately predict power consumption early in the design process. Many high-level power analysis tools don’t adequately model activity, however, leading to inaccurate results. In a previous publication, we introduced architecture-level power analysis techniques for datapath and memory modeling. This paper focuses on the control path, describing a novel power analysis strategy known as the Activity-Based Control (ABC) model. Architecturelevel estimates are then compared to switch-level simulations of three chips: a divider, a speech recognition controller, and a microprocessor. The average error observed in the control path power estimates is 13% with a maximum error of 29%.

An integrated CAD environment for low-power design

This CAD environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. An integrated set of analysis and optimization tools spans the design hierarchy, allowing the designer to make a systematic, top-down exploration and refinement of solutions in the area-time-power design space. In a case study-a low-power implementation of a digital bandpass filter-the CAD environment and tools yield more than an order of magnitude savings in power.

A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.

Algorithm and Architectural Level Methodologies for Low Power

With ever increasing integration levels, power has become a critical design parameter. Consequently, a lot of effort has gone into achieving lower dissipation at all levels of the design process. It has been demonstrated by several researchers that algorithm and architecture level design decisions can have a dramatic impact on power consumption [25][27]. However, design automation techniques at this level of abstraction have received scant attention. In this chapter we explore some of the known synthesis, optimization and estimation techniques applicable at the algorithm and architectural levels. The techniques mentioned in this chapter are targeted for DSP applications but can readily be adapted for more general applications.