Richard Gu

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.

A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver

Fiber Channel networks, gigabit Ethernet backbones, and IEEE 1394.b Firewire links require a high-speed point-to-point connection. This CMOS serial link transceiver dissipates 250 mW and has low jitter (8ps RMS, 44 ps P-P at 3.5 Gb/s), and wide frequency range (0.5-3.5 Gb/s). This transceiver is essential both for stand-alone and for standard-cell in a CMOS standard cell library.

A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.

Fractional-N phase locked loop design and applications

This paper presents fractional-N sigma-delta phase locked loop (PLL) applications and design. Applications focus primarily on wireless communication and clock synthesizers. Fractional-N PLL architectures are described in detail. The performance of multi-stage noise shaping (MASH) and single-loop sigma-delta modulators is compared. Constraints on PLL loop bandwidth while using sigma-delta modulators is discussed. The causes of fractional spurs and spur reduction techniques are demonstrated.

Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2 dBc/Hz at 10 MHz offset of a 56.2 GHz carrier and a tuning range of 9.1% (FOMT of -179 dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10 MHz offset among all the QVCOs around 50-60 GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76 GHz VCO and a 90 GHz VCO, both fabricated in a 65 nm CMOS process, with an FOMT of 173.6 dBc/Hz and 173.1 dBc/Hz, respectively.

54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique

This paper presents a novel topology of low-noise amplifier (LNA) with noise reduction and gain improvement. A transformer feedback gm-boosting technique is proposed in a single-ended cascode LNA to reduce the noise figure (NF) and improve the gain simultaneously. Two 54 GHz single-ended cascode LNAs, with transformer and transmission-line for matching, respectively, are demonstrated to verify this technique. Fabricated in a 65 nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best noise figure and power gain among all the published V-band CMOS LNAs. The transmission-line-based (TL-based) LNA exhibits a minimum noise figure of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement. Both the LNAs consume 18 mA from a power supply of 1.1 V.

A 6.25GHz 1V LC-PLL in 0.13/spl mu/m CMOS

A 6.25GHz PLL with integrated LC-tank VCO, on-chip loop filter and quadrature outputs is fabricated in 0.13mum CMOS technology. Operated at 1V supply with 62.5MHz input reference clock frequency, an output clock jitter of 0.5psrms is achieved by using a charge pump with rail-to-rail operation and leakage-current cancellation

An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS

A 6.25 GHz PLL with an integrated LC-tank VCO designed and fabricated in 0.13 mum CMOS technology is described. For a deep submicron CMOS technology, leakage currents and limited voltage headroom degrade PLL performance. This paper introduces a new charge pump design with rail-to-rail operation and leakage cancellation techniques to overcome these constraints. Operated at 1 V supply voltage with an input reference clock frequency of 62.5 MHz, the PLL has 0.5 ps rms jitter at output frequency of 6.25 GHz

Programmable termination for CML I/O's in high speed CMOS transceivers

This paper describes I/O circuits that can be used in high-speed transceivers to communicate with next generation and legacy devices. We describe the transmitter and receiver front-end circuits that are designed to operate with dual termination voltage supplies. The receiver characterization, ESD protection and system level power up issues related to gate-oxide and electro-migration reliability are discussed.