Paul F. Ferguson

One bit higher order sigma-delta A/D converters

A topology for higher-order sigma-delta modulations is described, and synthesis equations are given which allow for the arbitrary shaping of the signal and quantization noise transfer functions. The synthesis procedure is similar to that of switched-capacitor filters and uses switched-capacitor design techniques such as dynamic-range scaling, impedance scaling, and circuit noise analysis. Placement of passband zeros for the optimization of the quantization noise transfer functions is discussed, and some results measured on a third-order test chip are presented. Simulated results on nonlinear stabilization of the loop are discussed. The need for simulating the analog front-end along with the digital filters to find the true dynamic range of the system is indicated.<<ETX>>

Multi-mode CMOS low dropout voltage regulator for GSM handsets

This paper presents a 1.8 V 400 mA multi-mode low dropout voltage regulator designed in a 0.25 /spl mu/m CMOS process. Multiple power modes are used to increase the efficiency of the regulator under both heavy and light loads. Under heavy loads, a high power driver with dynamic current bias and a DC/DC converter are used to improve the efficiency from 50% to 75%. Under light loads, a low power driver is used to improve the efficiency from 0.2% to 43.5%.

An 18 b 10 mu s self-calibrating ADC

A self-calibrating, 18-b, serial-output, 100-ksample/s analog-to-digital converter (ADC) which is implemented on a 24-V BiCMOS analog chip and a 5-V, 2- mu m CMOS digital chip is described. This partitioning allows a larger input signal for better dynamic range, eases the comparator design, and protects analog circuitry from digital feedthrough. The two chips are wired in a 7.6-mm-wide, 16-pin plastic dual inline package (DIP). Thirteen inter-chip bonds make up the control and data interface. The only other common connections to the logic supply and its ground return are made through separate wires for each chip. The analog chip is a charge-balancing converter consisting of an 18-b calibrated digital-to-analog converter (DAC), an auto-zeroed latching comparator, buffers for all analog inputs, and logic for the self-timed interface to the digital chip. The digital chip is a custom microcontroller which implements the calibration aid conversion algorithms, as well as the digital part of the user interface. The data path on this chip includes calibration pattern generators, a successive approximation register (SAR), elements for calculating the error terms, and RAM for storing those terms.<<ETX>>

Session 16 overview: Gigahertz data converters

Circuit and architectural innovations have enabled medium and high-resolution data converters to push bandwidths beyond 1GHz. This entire session is devoted to gigahertz data converters covering resolutions up to 14b and sampling rates up to 10GS/s. The ADC papers in this session make extensive use of dynamic amplifiers and comparators, calibrations for offsets, timing, gain errors and transfer functions, and randomization techniques. An oversampled continuous-time pipeline ADC architecture combines the wide bandwidth of a pipeline ADC with the antialiasing properties of a continuous-time oversampling converter. The DAC papers employ mixing techniques in the analog or digital domains for direct up-conversion up to 21GHz.